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To: fingolfen who wrote (137158)	6/11/2001 6:39:02 PM
From: Dan3	Read Replies (1) \| Respond to of 186894

Re: What are the gate critical dimensions for the TSM and VIA processes? I'm betting that 0.13 micron for TSM is essentially similar to Intel and/or AMD's 0.18 micron processes. What happened to the .13 gates you said AMD was using in its .18 process last week? Did they switch back to .18? :-) Dan

To: fingolfen who wrote (137158)	6/11/2001 10:30:30 PM
From: milo_morai	Read Replies (2) \| Respond to of 186894

TSM Process TSM's 130nm process eetimes.com By default, LSI Logic will migrate to the Black Diamond low-k interconnect used by TSMC. Black Diamond has a k-value of 2.9, and is applied to a wafer using a chemical vapor deposition tool from Applied Materials Inc. Previously, LSI Logic had used low-k materials with a k-value of 3.1, Vasishta said. TSM eetimes.com There are several reasons why the foundries are crowing: *Their poly gate lengths at the 0.13-micron node are now below* 100 nanometers**, which helps bring gate delays down to 10 picoseconds. Gate densities, meanwhile, now exceed 200,000 gates/mm2. They have successfully integrated low-k dielectric insulator materials between copper metal interconnect, bringing the effective RC delay for interconnect down by 20 percent or more. --------------------------- Via Guess I'm out of date Via at 130nm now using TSM's process via.com.tw Intel's interesting article on MOS scaling developer.intel.com And on IBM's NanoTubes "Consequently, IBM said, it now appears that smaller carbon nanotube transistors could enable Moore's Law to continue even when the chip industry hits the limitations of silicon materials. " siliconstrategies.com