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To: George Dawson who wrote (3406)	6/12/2001 12:25:57 AM
From: Douglas Nordgren	Respond to of 4808

George, as innovative as BlueArc's PLD approach is, it remains to be seen if the company can build, supply, and service a sizeable customer base. In the meantime, the more things change, the more things change, however slowly. LSI, partners dial programmable core into ASICs By Brian Fuller EE Times (06/11/01, 8:35 p.m. EST) SAN FRANCISCO ? LSI Logic Corp. backed up two years of talk Monday (June 11) by rolling out details of a reconfigurable programmable logic function in an ASIC with partners Adaptive Silicon Inc. (ASi; Los Gatos, Calif.) and Ericsson. The details on the architectural approach were announced today, while LSI engineering manager Neal Stollon and Ericsson principal engineer Björn Sihlbom are scheduled to discuss a broadband implementation called Bazil at the Embedded Processor Forum in San Jose on Wednesday. The Liquid Logic programmable function is designed to give designers the flexibility to partition a block of their system-on-a-chip (SoC) that may need to be reprogrammed later to meet changing standards or customer specifications. It turns up the heat in the years-old scrap between low-end ASICs and high-end programmable logic solutions, the latter of which is intended to give EEs just that type of flexibility. "By incorporating reconfigurable logic on an SoC platform, new types of products become feasible," said Ronnie Vasishta, LSI's vice president of technology marketing. LSI and Ericsson Wednesday will detail an ASIC targeting third-generation (3G) wireless applications that includes an LSI ZSP digital signal processing core with the Liquid Logic core functioning as a slave coprocessor. ASi first drew notice almost two years ago when LSI Logic revealed plans to provide small programmable cores of less than 50,000 gates inside its ASICs. The idea of combining standard-cell logic with a programmable array has been a hot topic in the semiconductor industry, most notably among FPGA suppliers, who have begun attaching fixed-function cores to programmable arrays. Actel Corp. (Sunnyvale, Calif.) is one FPGA supplier that has announced its intent to produce a programmable ASIC core. At the heart of the architecture is a multiscale array that is composed of 4-bit configurable arithmetic logic units (ALUs); each of those ALUs' "bit-slice" is a function cell. Four ALUs form a quad block, roughly 1,500 ASIC gates. This manageable architecture is a nod to what ASi officials have said: that the real need for programmability is in the 10,000-to-15,000-gate range. "We're rewriting the rules from the ASIC point of view," said Peter Gasperini, LSI technical marketing manager for the Liquid Logic core. Another consideration in pushing the architecture on the masses is making sure it hews to an ASIC methodology. To that end, the core has been integrated into LSI's FS 3.0 flow, leaning heavily on ASi's Millennium PLC Ver. 1 tools. Designed to employ Synopsys' Design Compiler tool, the methodology moves the designer through synthesis, clocking, test, verification and layout down to timing closure. This last step, Gasperini claims, is a key in the approach. The Liquid Logic core is "decoupled" from the ASIC; the timing closure can be handled separately, driven from the ASIC circuitry into the array. LSI, which owns a portion of Adaptive Silicon, sees the Liquid Logic core as a way for designers to maintain the flexibility of a programmable-logic approach but hit high-volume markets where programmable-logic device solutions can lose their economic benefits. "It also expands the definition of applications for which the core is suitable," Gasperini said. While communications is a natural target market, so too will be consumer electronics, printers, storage-area-networks and other types of mass storage, he added. The architecture is targeted to LSI's G12 0.18-micron process. It will be available on the company's Gflex 0.13-micron process next year, Gasperini said. Additional reporting by Peter Clarke. eet.com