To: Paul Engel who wrote (137896 ) 6/21/2001 7:35:57 PM From: puborectalis Read Replies (2) | Respond to of 186894 Intel Aims for 20GHz Microchip in 2007, Executive Says June 21, 2001 (TOKYO) -- Robert S. Chau, Intel Corp.'s director of Transistor Research (Logic Technology Development), discussed the technical details of Intel's new MOS transistors featuring 0.02 micron technology. Chau said that Intel has confirmed the operation of the new transistors with the 0.02-micron gate technology. "This will allow Intel to realize a microprocessor integrating a billion transistors and run at a speed of 20GHz in 2007," said Chau. Within the industry, it was believed that the semiconductor structures with the gate length of less than 0.1 micron could not operate as a transistor because the gate oxide layers, which are composed of silicon-oxide (SiO 2 ), become excessively thin and consequently the tunnel-current inside the insulation layers becomes too large. Recently, many trials have been made to develop high-K dielectric materials to be substituted for gate oxide layers. This is because using high-K dielectric material will make thicker insulation layers. This time, Intel Labs produced the experimental transistors using the same structure and materials of current gate-oxides, and their insulation layers' thickness was 0.8 nanometer (0.0008-micron). The thickness of 0.8 nanometer is as thin as just three atoms in a row. By confirming the experimental transistor operations, Intel demonstrated that the conventional transistors and new transistors with the 0.02-micron technology have similar switching characteristics as those integrated into Pentium 4 chips and 256Mb DRAMs, and can be used for digital ICs. Massive Integration on a Chip If it is possible to design, test and manufacture such high-density and large-scale LSIs, this process technology would allow IC makers to commercialize LSIs with 1 billion transistors. A simple calculation shows the density, which would be equal to 25 Pentium 4 chips integrated into one LSI. Operation tests of the newly developed n-channel MOS transistors were done under drain voltage, which corresponds to a power supply voltage, of 0.75V, and gate threshold voltage, which shows the voltage point where the drain-current takes off, turn out to be 0.2 to 0.25V. According to Chau's announcement, the "short-channel-effect," in which the gate threshold voltage level changes largely depending on the gate length dispersion, has not been detected. Among the current mobile Pentium III series, Intel has a low-power dissipation version, in which the products operate with lower supply voltage of 1.1V. Power dissipation of an LSI is proportional to the square of supply voltage. Therefore, to reduce the LSI power dissipation, it's quite effective to lower the supply voltage. This time, as Intel confirmed, the transistor operation with the drain voltage is as low as 0.75V. "By integrating the transistors with 0.02-micron gate length, it allows us to design lower power dissipation LSIs," Chau said. According to the roadmap of Intel's installations of the new process technologies, the introduction the 0.02-micron gate length process will be in 2007, as shown in the table. At the new process, Intel plans to use the transistors of 0.02-micron gate length, and the 0.45-micron photolithography design rule. Intel's semiconductor roadmap Process Name P854 P856 P858 Px60 P1262 P1264 P1266 P1268 Year of Installation 1995 1997 1999 2001 2003 2005 2007 2009 Photo-Litho. Tech. (micron) 0.35 0.25 0.18 0.13 0.09 0.065 0.045 0.032 Gate Length (micron) 0.35 0.2 0.13 0.07 0.05 0.03 0.02 0.016 (Kenji Tsuda, Chief Technical Editor, Nikkei Electronics Asia)