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To: Jdaasoc who wrote (75011)	6/27/2001 12:50:54 PM
From: Ian Anderson	Read Replies (1) \| Respond to of 93625

Hold time is the time a data signal has to be stable after the clock edge in order to be sure that it's value is correctly saved in a memory element such as a latch or flip-flop. Designers normally regard zero hold time as the goal. Negative hold time simply means that it is OK for the data to change a short time before the clock edge, the previously stable value will still be stored.

To: Jdaasoc who wrote (75011)	6/27/2001 4:42:38 PM
From: Bilow	Respond to of 93625

Hi Jdaasoc; Re negative hold time and DDR... The article you link to provides a description of an alternative technique for hooking up a memory controller to DDR SDRAM. (1) The usual technique for getting data out of a DDR SDRAM is to use the clock provided by the DDR SDRAM to register the data. That clock is synchronous with the data, but it isn't synchronous with the system clock. After registering the data with the DDR clock, the chip has to resynchronize the data to the system clock. This requires a "clock domain transfer" circuit, and this increases latency. (Note that the same thing happens with RDRAM, but if the clocks are run the way they are in most systems, the clock domain transfer circuitry has to exist inside the RDRAM chips.) If you use the DDR clock, the DDR data will arrive before the clock, then the clock will rise, and then the DDR data will go away after the clock. The fact that the data goes away after the clock means that the DDR data has "positive hold time". The alternative technique is to ignore the DDR clock, but instead use the system clock (i.e. the one provided to the DDR chip) to clock the data. (I'm guessing that this is the way that Nvidia uses with their graphics chips.) DDR chips include a DLL (sometimes called PLL) circuit that aligns their internal clocks in such a way that it acts as if there is no propagation delay for the clock driver inside the chip. (This is a very common design technique, and it was one of the claims that Infineon was sued by Rambus on.) As a result of this DLL circuit, the data read from a DDR chip changes at about the same time as the clock rises (or falls) at the DDR chip. *This means that if you want to read the data, you have to be compatible with a negative hold time.* Almost every "flip-flop" (i.e. simple memory storage device) has a positive hold time requirement. This means that the data must remain valid for a positive length of time after the clock changes. But in order to use DDR in the alternative design technique, you will have to build a flip-flop (actually 64 of them, if that's the width of your data bus, or possibly twice that depending on what you do with the doubled data) that has a negative hold time. The simplest way to create a flip-flop with a negative hold time is simply to add a delaying circuit to the data, then hook up a standard flip-flop so that it samples the output of the delay. But delays in silicon are very difficult to guarantee for worst case design. So Micron gives a few other design techniques that will achieve a negative hold time flip-flop. One of the results of using DDR in this alternative (synchronous) design technique is that you will not have as long a period of time where the data is guaranteed to be valid. This means that the system design has to be tighter at the controller side, which is why it is a natural for graphics memory. Eventually, when most memory is soldered onto the motherboard, DDR will likely be used in synchronous fashion, and the system latency will be reduced. All in all, negative hold times and DDR are just another detail about a design you really shouldn't care much about, anymore than you care about how the arc welding robots put together the parts of the car you drive. -- Carl