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To: Jdaasoc who wrote (75386)	7/6/2001 6:16:15 PM
From: Scumbria	Respond to of 93625

John, The bottom of the article answers your question: Three memory-module slots support up to 512-MB of 100/133-MHz bus system memory.

To: Jdaasoc who wrote (75386)	7/10/2001 12:23:15 AM
From: Bilow	Respond to of 93625

Hi all; 6.4GB/sec bandwidth at SiByte's new processor uses DDR SDRAM: SiByte was bought by Broadcom (BRCM), who also bought ServerWorks. Funny thing is that ServerWorks is making DDR chipsets for servers. FAQ What are the details behind SiByte's scalable multi-processor SOC architecture? ... DDR memory controller ... What are the key features of the first Mercurian processor, the SB-1250? ... DDR memory controller ... sibyte.com Let's look at some details with this chip: DRAM Controller * Two channels each with a 64-bit databus plus ECC * DDR SDRAM, DDR SGRAM, Fujitsu FCRAM * Up to four JEDEC DDR DIMM slots * Up to 200 MHz clock (400 MHz data rate) ... DDR Memory Controller ... The SB-1250 can drive 1-4 JEDEC standard 184-pin unbuffered DIMMs for the lower speed (133-150 MHz clock rates [i.e. 266-300MHz data rates] ) DDR SDRAMs. For higher performance (150-200 MHz clock rates [i.e. 300-400MHz data rates] ) SGRAM and FCRAM systems, the memories must be mounted on the main PCB and careful control of the point-to-point traces between the SB-1250 and the DRAM chips is required. The memory controller has two channels (with separate address/control, 64-bit data and ECC signals) that may be run interleaved or as separate memory areas. ... The SB-1250 is available in a 860-pin EBGA 1mm pitch package. Estimated power dissipation at full speed with all interfaces in use is 8-10W. ... sibyte.com -- Carl P.S. to John: Note the unbuffered DDR memory utilization.

To: Jdaasoc who wrote (75386)	7/10/2001 1:48:30 PM
From: Bilow	Read Replies (1) \| Respond to of 93625

Hi all; Phillips to support 333MHz registered DDR DIMMs: DDR support components trim module height 30% EETimes via NewsEdge, July 10, 2001 Support registers and phase-locked loops that are able to support 333-MHz double-data-rate (DDR) performance are available from Philips Semiconductors in extra-small TSSOP and TVSOP packages. The support components are said to maximize DDR performance while minimizing power and board space in high-end server and advanced computing applications. With the parts, manufacturers can reduce the height of DDR modules by up to 30 percent. "Taking 1U DDR modules from 1.7 inches to 1.25 inches means system designers can achieve significantly heavier module stacking, freeing up vital real estate," said Pierre-Yves Lesaicherre, general manager of Philips' PC-motherboard IC product line. The PCKV857 70- to 190-MHz differential 1:10 SDRAM clock driver and SSTV16857 14-bit SSTL_2 registered driver are available in volume in the TSSOP-48 and are sampling in the TVSOP-48. Prices in quantities of 100,000 are $1.80 and $1.70, respectively. The SSTV16859 13- to 26-bit SSTL_2 registered driver for stacked DDR DIMMs is available in volume in TSSOP-64 packages, priced at $2.40. The PCKV856 70- to 190-MHz I2C differential 1:10 SDRAM clock driver and SSTV16856 14-bit SSTL_2 registered driver/buffer are sampling now in the TSSOP-48 package, priced at $2.00 and $1.90, respectively. ... manufacturing.net John: The 14-bit registered SSTL_2 drivers are the difference between unbuffered and registered DDR DIMMs. Note that they cost only $1.70 each. For a 64-bit plus ECC DDR DIMM, you'll need 6 of these puppies for a total change in BOM of $10.20. These are the latest parts and carry a slight premium to the older (and larger) parts. The low cost of this "popcorn" logic is why Crucial is able to sell registered DDR DIMMs at such a small premium to their unbuffered DDR DIMMs. -- Carl