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To: Tenchusatsu who wrote (139145)	7/12/2001 4:42:19 PM
From: maui_dude	Respond to of 186894

Tench, Re : "I think interconnect lengths don't necessarily shrink as much as feature sizes. So I don't think the die size will shrink as much as you expect." you are right, but for a different reason. The ratio of minimum width for interconnect is roughly the same in 0.18->0.13 as it was in earlier process transition. However, due to other additional requirements (Electromigration, self-heat, more decaps, repeaters etc) on .13 (and future processes), there is growth, resulting in not as much reduction in area. Maui.

To: Tenchusatsu who wrote (139145)	7/12/2001 5:25:48 PM
From: dale_laroy	Respond to of 186894

>I don't think the die size will shrink as much as you expect.< According to AMD's charts, the die size of the 0.13-micron Palomino?? will be 80mm2, versus 128mm2 for the 0.18-micron Palomino. This would translate to a 37.5% reduction in area going from 0.18-micron copper to 0.13-micron copper. In addition to smaller die gaining less from a design rule shrink, I would expect Intel to do even better going from 0.18-micron aluminum to 0.13-micron copper. A 37.5% reduction would yield about 136mm2 for Northwood. Additionally, while it is hardly any more guaranteed than Intel's presumed gain in frequency from Athlon like pipeline tweaks, Intel could realize a K7 to K75 like relayout shrink. In going from 0.22-microns for the K7 to 0.18-micron for the K75, a shrink that would have yielded only a 32% reduction from an optical shrink, actually yielded about a 44% shrink from 184mm2 to 102mm2.