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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: dale_laroy who wrote (139287)	7/15/2001 9:27:19 PM
From: Elmer	Read Replies (1) \| Respond to of 186894

Doubling the size of the L2 cache would, at most, double the defect rate. The defect rate is a function of the process, not the device, and it is not necessarily constant across all structures. Given AMD's problems with large L2s, it is fair to assume the sram arrays have a higher defect rate than the other structures. Therefore doubling the L2 size could very well more than double the trouble. Actually, if we were to assume that 29% of AMD's desktop Palomino processors were to have one or more defects that forces AMD to salvage them as mobile Morgan processors, this should be quite adequate to meet demand for mobile Morgan processors. Yet this would extrapolate to a 50% yield of good processors with 512KB L2 cache. I don't know where you are getting these numbers from but I don't think they're accurate. AMD may already be having problems yielding with 256K L2 so your assumption that they would get 50% yield with 512K is a bit much. It is more likely they would get very low yield at 512K or they would be doing it already. The die size would also be prohibitive on their current process. With the shrink to 0.13-micron the yield of fully qualified 512KB Thoroughbred processors could far exceed 50% of the total shippable Thoroughbred processors AMDites should give up hope of this, but there's always the power of prayer. EP