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To: Paul Engel who wrote (139695)	7/19/2001 12:28:25 PM
From: Dan3	Read Replies (1) \| Respond to of 186894

Re: AMD is ALREADY using sub 0.09 micron transistors (Leff) on their 0.18 micron Actually, although AMD doesn't let out much regarding their new process, their FAB technology partner Fujitsu is a bit more forthcoming: Look at these data on what Fujitsu refers to as the ".11 generation"... Fujitsu Microelectronics, Inc. (FMI) today introduced its new 0.11 micron gate length (0.11um Lgate) ASIC process capability, featuring the industry's lowest power, fastest transistors and most compact memory cells. Fujitsu's 0.11 micron technology (0.07 micron Leff), which will be available by the third quarter of 2001, features shallow trench isolation (STI) techniques, chemical-mechanical polishing (CMP) for all planarization and CoSi2 in transistor gate and source/drain. The all-layer copper-interconnect process uses five to eight levels of metal and low-k (k <= 2.6) dielectric techniques. Initial products developed using the very deep submicron process will support devices with as many as 56 million gates per chip. The gates will be characterized at 0.85V to 1.65V, with analog and I/O blocks to be available in both 2.5V and 3.3V. The junction temperature range is -40(degrees)C to 125(degrees)C. Densities are twice those of ASICs manufactured using Fujitsu's 0.18 micron process technology. The power requirements for Fujitsu's 0.11 micron process are 2nW/MHz/gate at 1.2V. The technology also features the industry's smallest memory cells, at only 2 micron squared (2 um2) for the 6-transistor SRAM and 0.2 micron squared for embedded DRAM. vr-zone.com Besides, leff isn't a very good measure to use (particularly in a discussion that used the "process generation" number everywhere else, but that's just your typical blithering). In the case of line widths there may however be some legitimacy to the different numbers they feed you. Each company uses a different definition for this parameter, and within the same Company they may bounce between definitions to suit their purposes. One definition is the drawn width of the minimum poly-silicon feature. Another definition is called Leff ('L' effective), the minimum length of the electrically isolated region under the CMOS transistor. The value in this second definition is modulated by the drawn width from the first definition. It, however, is also modulated by diffusion of ions implanted into the silicon substrate which often makes it 15% to 40% smaller then the drawn width. This definition is also highly dependent on the algorithm and the equipment used to calculate the Leff parameter. geek.com