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To: Jdaasoc who wrote (76126)	7/24/2001 3:43:18 PM
From: Win Smith	Read Replies (1) \| Respond to of 93625

I don't know about Carl, but Scumbria is somewhat on record on that matter. Message 14146381 Of course, since the Yahoosiers seem to have reprogrammed Scumbria's latency since then, they may have also programmed a new definition of Scumbria's TLA. Who knows?

To: Jdaasoc who wrote (76126)	7/24/2001 4:05:06 PM
From: Scumbria	Read Replies (1) \| Respond to of 93625

John, I'm not a lawyer and don't understand how they think. The programmable latency register formerly resided in the memory controller. The advent of SDRAM sent that and some other logic over to the DRAM chip. It doesn't seem like a big deal from an engineering point of view, but it has kept a lot of lawyers and judges busy for the last two years. How it will ultimately be resolved is anyone's guess.

To: Jdaasoc who wrote (76126)	7/24/2001 5:11:15 PM
From: John Walliker	Read Replies (2) \| Respond to of 93625

John, This patent is about much more than just memory. It provides a framework for interconnecting all the main components of an embedded system, including multiple processors. It is clearly aimed at applications where small size, high speed and low power consumption are important. Existing designs might use a number of different processors, each with its own memory interface to ram and flash eprom, and then interconnect them with i2c, spi or other narrow point-to-point or bus interfaces. It differs from RDRAM in that it does not support bus lengths greater that the flight time of one bit, but it does support multiple bus masters. John