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To: Tenchusatsu who wrote (140416)	7/30/2001 12:43:59 AM
From: Dan3	Read Replies (1) \| Respond to of 186894

Re: I/O devices typically access memory directly instead of relying on processors to provide them data. Pretty much the whole point. On Athlon's point to point chipset, while the CPU is bursting bytes out to a NIC buffer, a DMA transfer can take place from the disk controller to RAM. On P4's bus chipset, it has to wait. Going from 8-way to 16-way isn't going to reduce cache thrashing that much On a big server with many processes, it will reduce it more than going from 256K cache to 2 meg cache, depending ont he software running.

To: Tenchusatsu who wrote (140416)	7/30/2001 12:54:29 AM
From: Dan3	Respond to of 186894

Re: I/O devices typically access memory directly instead of relying on processors to provide them data. Pretty much the whole point. On Athlon's point to point chipset, while the CPU is bursting bytes out to a NIC buffer, a DMA transfer can take place from the disk controller to RAM. Saturating a gigabit NIC is not a trivial use of bandwidth. On P4's bus chipset, it has to wait. The Athlon system can move data from disk to RAM and from CPU to NIC concurrently, while the two operations contend for the single memory bus on P4. Is it worth 5% in overall performance? 15%? It will depend on the application, but in many cases it will be as important as the move from 256K cache to 2meg cache - and a lot cheaper. Going from 8-way to 16-way isn't going to reduce cache thrashing that much On a big server with many processes, it could reduce thrashing more than going from 256K cache to 2 meg cache, (depending on the applications). In some case it will be unimportant, in others crucial.