Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Dan3 who wrote (140426)	7/30/2001 9:46:11 AM
From: GVTucker	Read Replies (1) \| Respond to of 186894

A little OT, RE: Wall St. analysts There's an excellent column on the editorial page of today's Wall St. Journal about the changing world of Wall St. analysts. Eventually, the column argues that the analyst will become extinct. It was written by Andy Kessler, who was a good analyst with both Morgan Stanley and PaineWebber a few years back and now runs a tech hedge fund in Palo Alto.

To: Dan3 who wrote (140426)	7/30/2001 10:09:53 AM
From: dale_laroy	Respond to of 186894

>On an AMD system, if one CPU is writing to (or reading from) memory, the other CPU can be reading from memory, NIC, Disk controller, etc.< So what? Traffic between the CPU and peripheral devices is quite low bandwidth. The high bandwidth is between the peripheral devices and memory, which does not involve the processor bus. >Or, even with only a single CPU, there could be a concurrent DMA transfer between peripheral and memory while the CPU is is updating a different region in memory< Without dual channel memory there can not be simultaneous access to main memory, even with a P2P processor bus, and with dual channel memory a DMA transfer between a peripheral and memory can be concurrent with a processor access to memory even without a P2P processor bus. >(there will be cases where there is contention for the same pages, but usually not).< If you want to decrease (indeed eliminate) contention for pages, the best approach is using VCM the way it is intended to be used. The memory controller would assign one way of buffers to the PCI bus, one way to the AGP bus, and one way each to each of the CPU's. Now, this is where a P2P processor bus could come in handy because, with a shared bus it would be more difficult unraveling which processor was accessing which way. But, then again, the 760 chipset does not support VC SDRAM. The FIFO buffers on each of the point-to-point busses will also allow for better utilization of the memory, I/O, and AGP busses. They act in a way that is similar to prefetch in a processor. The benefits are limited with a single DDR 2100 channel, but will scale nicely with DDR 2400, DDR 3200, etc. while P4 hits a wall with its single bus. Obviously, Athlon's bus will also take much more advantage of any dual channel configuration than P4's, too.

To: Dan3 who wrote (140426)	7/30/2001 1:06:23 PM
From: Tenchusatsu	Respond to of 186894

Dan, <On an AMD system, if one CPU is writing to (or reading from) memory, the other CPU can be reading from memory, NIC, Disk controller, etc. Or, even with only a single CPU, there could be a concurrent DMA transfer between peripheral and memory while the CPU is is updating a different region in memory (there will be cases where there is contention for the same pages, but usually not).> Please, Dan, GIVE IT UP. You continually make up false statements and utter them with a straight face. First you claim that it's important that CPU-to-I/O accesses are independent of CPU-to-memory. Then you claim that CPU-to-I/O can occur at the same time as I/O-to-memory. Now you claim that CPU-to-memory can occur at the same time as I/O-to-memory. It doesn't matter whether the accesses are on different pages or not. All that allows is pipelining of accesses, i.e. hiding latency behind a previous transaction. There is still only ONE memory channel in the dual-CPU chipsets we are talking about. Only one transaction can be transferring data at a time. And besides, NONE of this has any relevance to the argument over P2P vs. shared buses. <The FIFO buffers on each of the point-to-point busses will also allow for better utilization of the memory, I/O, and AGP busses. They act in a way that is similar to prefetch in a processor.> Then by your own words, this is a useless feature, because it's better to have the processor prefetch for itself than to have the chipset do it for you. The only use a prefetch buffer may have on a chipset is use of spare memory bandwidth, which is obviously not the case for the 760MP chipset. <The benefits are limited with a single DDR 2100 channel> Ah, you finally understand. Too bad your admission is mixed in with your continued lies. <but will scale nicely with DDR 2400, DDR 3200, etc. while P4 hits a wall with its single bus.> You are talking about potential vs. reality. The "potential" for P2P buses is great, especially EV6 and HyperTransport. The reality is that AMD just isn't there yet and probably won't be for quite a long time. As for "hitting a wall," I think you need to get your depth perception checked. Shared buses still have a lot of life left, and you'll be surprised how far Intel can take it. <Obviously, Athlon's bus will also take much more advantage of any dual channel configuration than P4's, too.> Obviously AMD will need to release a platform with multiple CPU interfaces and multiple memory channels. nForce doesn't cut it because it only has one CPU interface. I see your method Dan. Spew every theory you can come up with and leave it to me to sort out the truth from the falsehoods. That'll probably work on the AMD cheerleaders forum, but not here. Tenchusatsu