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To: Tenchusatsu who wrote (140535)	7/31/2001 12:48:30 PM
From: Tony Viola	Respond to of 186894

Ten, This is the myth perpetuated by people who think they've become instant experts in servers just by reading a few HyperTransport foils. Going to 4-way and above with HyperTransport isn't as simple as putting together a bunch of Legos. It's a big deal to support the BIOS, design a motherboard, get OEMs to validate it, get OS support, make sure it's compatible with existing 4-way-enabled software, etc. The old saw "anybody can build just one" may apply here. I think you and Intel are working on chips for servers that people like B of A might use. The other extreme, like the lashups our friend is talking about, might power on in a few university labs, but not in Fortune 500 companies. Speaking of B of A, sounds like they're talking up Intel today, somewhere: Message 16149889 Tony

To: Tenchusatsu who wrote (140535)	7/31/2001 2:17:01 PM
From: pgerassi	Read Replies (2) \| Respond to of 186894

Dear Tony: You seem to assume that the lessons learned in going from 1 link to 2 links are not applicable to going from 2 to 4. Loosely coupled SMP system applications are well understood. AMD seems to be going in a straight forward manner. Its next step is to connect the NB and SB by HT. This will be soon in production (if not already from Nvidea). The next step after that is to put the AGP in between the NB and the SB (NB-HT-(CHIP-AGP)-HT-SB (that allows the current AGP port to be changed to a HT port). Then integrate NB with CPU (Clawhammer)(converting the HT port to going 2 way for this CPU). Then do it for MPNB (Sledgehammer)(adding as many HT ports as required for N way). Concurrently converting the AGP interface chip to connect to PCI 64/66, another to PCI-X and all other desired I/O busses. Each step level taking 6 months to work out the bugs. AMD seems to want to go to using standard chips to act like building blocks to make scaling simple and straight forward. It is a good plan. The protocols are known and can be retuned for maximum performance once it works. For N way SMP, communications designs were used by all the major OEMs for 8 and up ways. The protocols are well known (just look at Beowulf clusters using ethernet switches as the fabric). AMD is going to use HT as the threads and the CPUs having integrated switches as the loom to make N way SMP CPU systems as fabrics. AMD is taking the next steps. They need them to go to 4 way but, taking the second step is not as hard as the first step. Once AMD gets to 4 way, going to N way will be far simpler than you think and Intel will be left far behind, if they do not try to go more than 8 way. Pete