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To: fyodor_ who wrote (49531)	8/1/2001 11:15:03 PM
From: Yousef	Respond to of 275872

fyodor, Re: "The transistor above shows a drawn gate length of ~50 nm (Lpoly)." Please read your first link more carefully --> chip-architect.com This says the AMD/Motorolo HiP7 process (.13um) will have an "effective" gate length of 80nm as compared to Intel's (already released .13um) 70nm. The "effective" gate length is the electrically extracted gate length that usually corresponds to the distance from Source to Drain. This is NOT the drawn gate length ... The drawn gate length is probably closer to 100 - 110nm. BTW, Intel's "effective" gate length is > 10% less than AMD/Motorolo's ... This means Intel will have higher drive current and better ability to lower the voltage (for mobile products) without losing as much performance. The 50nm picture is of "future development" ... This means NOT .13um but probably .10um or beyond. This is usually used for "marketing hype". <ggg> Hope this helps. Make It So, Yousef