SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?


To: Paul Engel who wrote (49953)8/5/2001 3:54:32 PM
From: ptannerRead Replies (2) | Respond to of 275872
 
Paul, you wrote "And your claim was that AMD gets ALL 350 DIE - in usable form !!!" to Dan3.

You are too quick on the attack on this one: Dan3's original post didn't say that all 350 of the 80 mm die would work. (http://www.siliconinvestor.com/readmsg.aspx?msgid=16170710)

The math in the original message assumed $2,000/wafer resulting in $8/die cost for standard process which implies only 250 working die per wafer ($2,000/$8=250). The SOI die cost of $14 implies $2,500/$14=178 working die/wafer.

Assuming 350 (Dan3 formula) to 300 (Jim McMannis) raw die per wafer would be yields ranging from 71-83% for standard process and 50-60% for SOI. Dan3's assumptions may be off but the point of his post seems valid: a 25% increase in wafer cost and drop in yields to 50% of gross (his raw wafer count) results in a near doubling of the cost per working die but this may be readily recoverable in higher selling price potential from the SOI product.

Sure the total revenues may hold up; however, I do have a different concern about using this process using the same assumptions above: will AMD have the production potential to supply their desired market share goal? The transition from 250 to 178 working die is 30% lower output for 0.13 SOI compared to 0.13 standard; further the 0.13 SOI working die values could be about the same as the current 0.18 process scale.

T-Bird: 200mm wafer, 120mm T-Bird, 221 raw die, 75-80% working yield, 166-177 working die/wafer
Palomino: 200mm wafer, 128mm T-Bird, 206 raw die, 75-80% working yield, 154-165 working die/wafer
Note: die/wafer formula = { (pi * r^2) / die area } - { (2*@PI*r)/@SQRT(2*die area) }

It seems SOI may not simultaneously lower heat and increase performance and further it may not increase chips/wafer. Does SOI also potentially slow down the production rate or do they use a longer fab "pipeline" so it just increases "latency" (start to finish time)? These are just questions from the discussion here and what little I have read elsewhere on the web.

-PT



To: Paul Engel who wrote (49953)8/5/2001 5:18:58 PM
From: Dan3Respond to of 275872
 
Re: AMD gets ALL 350 DIE - in usable form !!!

Very unlikely - that would result in a die cost of $5.60.

You'll note that I estimated $8 to $12. In other words, my estimates accounted for the possibility that yield losses and SOI costs might more than double the cost of a perfect yielding, non-SOI wafer.