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Technology Stocks : Son of SAN - Storage Networking Technologies -- Ignore unavailable to you. Want to Upgrade?

To: David A. Lethe who wrote (3760)	8/5/2001 8:40:05 PM
From: Gus	Read Replies (1) \| Respond to of 4808

C'mon David. Everybody has been using that single-point-of-failure argument against Symmetrix and its global cache architecture since it first came out in 1990 and that hasn't stopped EMC from developing an installed base for Symmetrix of more than 45,000 units. People often forget that Dick Egan developed the critical memory subsystem for the Apollo Mission Guidance Computer program in the sixties. It should come as no surprise then that EMC has always remained at the leading edge of cache subsystem design. Anyway, the current Symms use a quad-bus segmented cache design. Each memory board contains up to 4 independent memory regions so four memory boards contain up to 16 independent memory regions. Each channel or disk drive director contains 2 microprocessors and connect to at least 2 memory boards. There are 4 to 8 Channel Directors and 4 to 8 Disk Drive Directors per Symm. Channel Directors create data paths between the cache and servers while Disk Drive Directors create data paths between the cache and disk drives. Anyway, these excerpts from the Symmetrix product guide should shed more light on this non-issue. CACHE MAINTENANCE ......EMC makes every effort to provide the most highly reliable hardware in the industry. However, all hardware is subject to the effects of aging and occasional failures. The unique methods used by Symmetrix for detecting and preventing these hard failures in a proactive way set it apart from all others in providing continuous data integrity and high availability. Symmetrix 8000 systems actively monitor I/O operations for temporary errors. By tracking these temporary, or soft, errors during normal operation, Symmetrix can recognize patterns of error activity and predict a potential hard failure before it occurs. This proactive error tracking can usually prevent an error in cache by fencing off, or removing from service, a failing memory segment before data errors occur. CACHE SCRUBBING Constant cache scrubbing to detect and correct single and double-bit errors dramatically reduces the potential for multi-bit or hard errors. In addition to monitoring recoverable conditions during normal access, all locations in cache are periodically read and rewritten to detect, and correct, single and double-bit errors. Symmetrix’s cache scrubbing technique maintains a record of errors for each memory segment. If the predetermined error threshold is reached, the segment’s contents are moved to another area in cache, and the segment is ‘fenced’ and removed from service. Should a multi-bit error be detected during the scrubbing process, it is considered a permanent error and the segment is immediately ‘fenced’. A Service Processor call home alerts EMC to the unacceptable level of errors and a non-disruptive memory replacement is ordered. A Customer Service engineer is dispatched with the appropriate parts for a speedy repair...... ADVANCED CACHING ALGORITHMS .....Simply having these robust cache configurations is not enough. One of the fundamental differences between Symmetrix products and all other data storage systems is the advanced caching algorithms that allow intelligent use of the installed cache for high performance. A potential problem with increasingly large cache configurations is that search time increases proportionally since this search time is added to every I/O request, read hit, read miss, or write. This is a considerable penalty for every I/O request, especially in performance-critical applications. In some data storage systems, the controller may actually disconnect from the channel during each search process and must then reconnect if there is a cache hit. Symmetrix systems perform the cache search via advanced proprietary algorithms, determining — in microseconds — if a record is in cache. As well as searching quickly and efficiently to determine whether the requested data is in cache, they also understand how the application is accessing the data and tune themselves accordingly in real time. These advanced algorithms allow the search time to remain constant regardless of application workload. With cache searches performed at electronic speed, there is no reason to disconnect from the channel during the search. In fact, it takes longer to disconnect and reconnect than it does to perform the cache search. In normal operation, the only time that a Symmetrix system will disconnect from the channel is in the event of a read miss. This is a complex series of tasks and requires the advanced cache management algorithms of Symmetrix to accomplish effectively. Symmetrix cache management is based on the principle that the working-set of data at any given time is relatively small when compared to the total system storage capacity. When this working-set of data is in cache, there is a significant improvement in I/O performance. The performance improvement achieved is dependent on both: • Locality of Reference — If a given piece of data is used, there is a high probability that a nearby piece of data will be used shortly thereafter. • Data Reuse — If a given piece of data is used, there is a high probability that it will be reused shortly thereafter. emc.com