Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: combjelly who wrote (50828)	8/12/2001 6:05:16 PM
From: Elmer	Read Replies (2) \| Respond to of 275872

Leffs typically wound up something close to 50% of the linewidths in a performance process, Al just poops out before Intel could do that. So AMD is closer to historical norms than Intel is. While I'm not a process expert I believe you have it wrong here. Channel lengths are not part of the copper process steps. Copper is for the interconnects while the channel lengths are the area below the gate oxide. To say that Al poops out is non-sequitur. Furthermore, I believe Paul is referring to physical channel lengths, not effective channel lengths and there is reason to believe AMD has already pushed their process to what one would normally call .13u dimensions. This is why people think AMD has already blown their .13u wad, so to speak. EP

To: combjelly who wrote (50828)	8/12/2001 7:07:29 PM
From: wanna_bmw	Read Replies (3) \| Respond to of 275872

Combjelly, Re: "Just out of curiosity, do you understand about pipeline stages in a processor?" Yes. In fact, I understood everything you said. But like Elmer has said in his response, you might be confusing the use of copper interconnects in a system. Now, I am not a process expert, either, but this is how I understand the situation. With more pipelines, you have a lower latency per pipeline stage, and thus you are able to clock your processor faster. However, signals from one logical unit to another sometimes travel over very long wires, and the wires themselves begin having a measurable delay at smaller processes. With aluminum, the capacitance of the wires causes a charging effect, which makes it take a longer amount of time before you get a stable logical value on the wire. With copper, this capacitance is reduced, and the wires themselves can switch faster. Depending on a lot of different variables on the manufacturing process, you could essentially get more mileage out of aluminum interconnects, and I believe that's what Intel had done, and it may have been cheaper or easier for them to do so at the time. Intel might have been able to get even more power from copper wires, but we'll never know, so there's no use in guessing over the possibility. "it very well may be that the AMD transistors switch faster" Actually, if AMD is using the much smaller gate width that you were talking about before, then their transistors probably are faster. At 180nm design processes, the gate width is typically 130nm, and at 130nm processes, the gate width can be as small as 70nm. If AMD's are 90nm, then they are using features close to what is found in a 130nm process, and this may be giving them the edge now to put 1.73GHz processors on their roadmap for their 180nm designed Athlon. "AMD can reach or exceed 3GHz with their Hammers..." If what I said above is true, then AMD is already getting some of the benefit of a 130nm process in their 180nm process. If SOI only provides a couple speed grades of improvement, my guess is that the K7 called Barton will probably max out at 2.4GHz. I'm also guessing that Hammer won't be much different than the K7 core with x86-64 and integrated Hypertransport channels. If that's true, then even an aggressive speed design won't get it to clock much higher than Barton. But then again, this is just my WAG. Your guess is as good as mine. wanna_bmw