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To: Ali Chen who wrote (51116)	8/14/2001 11:57:59 PM
From: Bilow	Respond to of 275872

Hi Ali Chen; Re: "What metrics ..." My calibrated eyeballs, of course, LOL!!! The EV6 uses fewer cycles to reverse between reading and writing. When you reverse a DDR SDRAM chip (or bank) from writing to reading, you lose 2 or 3 cycles (each cycle is two transfers) of data due to the CAS latency time. When you reverse it the other way, you lose 1 cycle of data. (The EV6 bus uses 1 cycle each way, I believe). Where the nForce will shine is in the reduced latency, as you hinted. Speculative prefetch is going to be helped considerably by the double DDR channels. -- Carl