To: Tenchusatsu who wrote (51416 ) 8/16/2001 4:42:21 PM From: wanna_bmw Read Replies (1) | Respond to Tenchusatsu, you are correct that the number of stages does not equate perfectly to the amount of headroom you will get with frequency, or the penalty you will get due to branch mispredictions. It's actually more dependant on how well these pipelines are balanced, so as to avoid one stage being longer than the others, and how well the branch prediction algorithms are, so as to minimize the number of pipeline stages that can incur a penalty. While are are astute enough to realize that the Pentium III and Pentium 4 both have additional pipeline stages that aren't advertised directly, I think by the same token, you are underestimating just how many pipeline stages the Athlon has. For example, when running a floating point instruction, the Athlon actually goes through 15 stages of operation.amd.com (page 204)Predicted-taken branches incur only a single-cycle delay to redirect the instruction fetcher to the target instruction. In the event of a mispredict, the minimum penalty is ten cycles. developer.intel.com (page 35)For Pentium 4 processor, the branch delay for a correctly predicted instruction can be as few as zero clock cycles. The branch delay for a mispredicted branch can be many cycles; typically this is equivalent to the depth of the pipeline. developer.intel.com (page 30)Branches that are not taken suffer no penalty... branches that are correctly predicted as taken by the BTB suffer a minor penalty of losing one cycle of instruction fetch... typically, the average number of cycles lost because of a mispredicted branch is between 10 and 15 cycles and possibly as many as 26 cycles.
