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To: E_K_S who wrote (44497)	8/17/2001 10:08:05 PM
From: Charles Tutt	Respond to of 64865

I think the comparison is more like a 250 MHz Pentium, which would itself perhaps be like a 100 MHz UltraSparc. JMHO. Charles Tutt (TM)

To: E_K_S who wrote (44497)	8/19/2001 5:11:29 AM
From: Joseph Pareti	Read Replies (1) \| Respond to of 64865

Re . The UltraSparc V will be able to switch between two different modes depending on the type of work the computer is doing. One mode will be good for heavy-duty calculations, the other for business transactions such as recording or retrieving information in a database. I guess the heavy-duty calculation mode will utilize a very efficient floating point processor and not a software translator found in Intels's current approach. Where can I buy it ? :-) Meanwhile I can buy UltraSlow III @ 750 MHz ------------------------------------------------- LINPACK 1Kx1k 1300 MFLOPS on UltraSlow III @ 750 MHz LINPACK 1Kx1k 2380 MFLOPS on ITANIUM @ 800 MHz SPECfp2K 373 on UltraSlow III @ 750 MHz SPECfp2K 711 on ITANIUM @ 800 MHz intel.com

To: E_K_S who wrote (44497)	8/20/2001 5:22:19 PM
From: Robert	Respond to of 64865

The Itanium/Merced/McKinley line run the IA-64 instruction set. The IA-64 instruction set is actually 128 bits, not 64. Of the 128 bits, there are 3 sets of 40 bit operations and one 8 bit template to specify interdependence between different words. IA-64 is not true VLIW but a hybrid VLIW-Superscalar architecture. Over time IA-64 and Sparc will converge architecturally as IA-64 adds more superscalar profiling to compensate for compiler and real time deficiencies and Sparc adds more CPUs on a single chip.