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Politics : Formerly About Applied Materials -- Ignore unavailable to you. Want to Upgrade?

To: Proud_Infidel who wrote (50979)	8/22/2001 7:53:55 AM
From: Proud_Infidel	Respond to of 70976

Intel Prototypes 0.02micron MOS Transistor Intel Corp has made a prototype 0.02micron gate n-channel metal-oxide-semiconductor (MOS) transistor (see Fig), which operates successfully. It has been said that MOS transistors with a gate length of less than 0.1micron may not operate normally, because the tunneling current flowing into the gate insulator increases due to the thinness of the gate silicon dioxide. Industry activity is moving towards developing a new gate material with a higher dielectric constant, replacing conventional silicon dioxide. The larger the dielectric constant, the thicker the gate insulator available. The new transistor has the same silicon dioxide as the gate insulator, with a thickness of only 0.8nm (0.0008micron), corresponding to a three-atom distance. Intel claims that the 0.02micron MOS transistor can operate in switching mode, as with the current most highly integrated chips, like the Pentium 4 or the 256-Mbit DRAM. Translator Chip If there are no problems with the highly-integrated chip design, and with testing and manufacturing feasibility, the 0.02micron transistor circuit means that one billion transistors can be integrated into a single chip. Today, the most highly integrated logic chip is the Pentium 4, with 42 million transistors. "The one billion transistor chip may function as a translator between Japanese and English, for example," says Robert S Chau, Intel Fellow and director of Transistor Research. The n-channel MOS transistor shows flat current-voltage characteristics in current saturation mode. With a drain voltage of 0.75V (which corresponds to a supply voltage) a gate threshold voltage of 0.2-0.25V is obtained. The gate threshold is the voltage that the drain current causes to flow. According to Intel, the transistor shows no short-channel effect; a variation of gate lengths between MOS transistors may extend a variation of gate threshold voltages. Concerning power dissipation, the company says the energy-delay is the product of 1 x 10 -29 Joules a second, which is a hundredth of that of existing 0.1micron transistors used in current cutting-edge integrated circuits. The switching energy means that it is equal to the dissipation power in switching, multiplied by the transistor delay time in switching. The product of power by time by time is therefore a hundredth that of the 0.1micron transistor. In an actual IC chip, power dissipation strongly depends on lowering the supply voltage V, because it is proportional to C (capacitor) x V 2 x f (frequency). According to Chau, reducing the supply voltage enables a lower power design for the one billion transistor IC. Roadmap to 2007 The Intel roadmap shows that a 0.02micron transistor process with a 0.045micron lithographic design rule will be introduced around 2007. In 2009, a 0.016micron transistor will be introduced with a 0.032micron design rule. The company is pushing forward to finer line technologies of less than 0.13micron: current work involves leading-edge ArF excimer laser lithography with a 193nm wavelength; next will come F 2 excimer laser lithography with 157nm wavelength; and further on will come soft X-ray extreme ultraviolet (EUV) lithography. Intel plans to work on finer line technology and a high dielectric constant material to ensure the gate insulator process margin, through alliances with universities and national research organizations, and with consortiums such as SEMATECH. Chau's laboratory already has a 300mm wafer pilot line installed, for a smooth and seamless transfer to a 300mm wafer production line. As for the strained silicon technology recently announced by IBM, many semiconductor firms have experience with this technology, which increases electron mobility due to a smaller effective mass under the strained silicon crystal. A thin silicon film on insulator (SOI) was showing higher mobilities from semiconductor firms a dozen years ago. Expressing "a private opinion," Chau said, "I think this announcement on the strained silicon is not something new. This is just the first announcement on the strained silicon from IBM." by Kenji Tsuda (August 2001 Issue, Nikkei Electronics Asia)