SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?


To: Ali Chen who wrote (52605)8/27/2001 2:47:31 PM
From: AK2004Respond to of 275872
 
Ali
re: delays in hammer
very possible but you have to admit that at one point amd should rely on its partners. Granted, it did not work very well in the past (via) but OTOH amd does not have the same resources as intel
Regards
-Albert



To: Ali Chen who wrote (52605)8/28/2001 11:32:25 AM
From: fyodor_Read Replies (1) | Respond to of 275872
 
Ali: I don't know performance of hammers. What I do know is
that usually the core design is separated from platform
design. The most brilliant core may totally suck if
plugged into a lame system.


With Hammers, the separation is apparently somewhat less, with the memory controller being moved on-die.

I assume communication with the "South Bridge+" will occur via HT, but I don't think we know for sure (although the upcoming µP conference in mid-October should reveal this and more).

One can only hope that AMD can manage to keep up with memory types and that the memory controller doesn't slow down the whole core.

I even afraid to predict that there will be delays in hammers due to same platform problems.

I think the risk of platform problems with Hammers is less, since "all" that is needed is a south bridge + AGP + HT to the processor.

-fyo