SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?


To: Elmer who wrote (142245)8/28/2001 2:14:14 AM
From: Cirruslvr  Respond to of 186894
 
Elmer - RE: "It's not claiming anything about future Intel products, just that it seems to make more sense for a larger L2 with the current L2 cache controller, rather than an L3 and an additional L3 cache controller added to an otherwise existing product."

I understand.. Either way, its gonna be one heck of a processor.



To: Elmer who wrote (142245)8/28/2001 10:37:01 AM
From: wanna_bmw  Respond to of 186894
 
Elmer, Re: "it seems to make more sense for a larger L2 with the current L2 cache controller, rather than an L3 and an additional L3 cache controller added to an otherwise existing product."

If you'll recall, the original design of the Pentium 4 called for an off-chip L3 cache, so they do not have to start from scratch for the cache controller. I believe that as it stands, the MP Xeon will have 512KB or 1MB of L3 on the chip. That's in addition to the 256KB of L2 cache. I think Tom's Hardware might have done an article on this before.

wanna_bmw