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To: andy kelly who wrote (142319)8/28/2001 7:32:32 PM
From: Tenchusatsu  Respond to of 186894
 
Andy, <the P4 chip is larger than anyone predicted because it has space devoted to JT, and it currently has lower IPC than might be possible because the cache size was reduced to accommodate the JT circuits?>

In the slides presented at IDF (thanks BMW), Intel says, "Two logical processors for very small additional die area." Most of the cost of HyperThreading is design complexity, not silicon.

developer.intel.com

Tenchusatsu