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To: wanna_bmw who wrote (52888)8/29/2001 12:21:43 AM
From: Dan3Read Replies (2) | Respond to of 275872
 
Wanna_bmw - do you know anything at all about how a cache works?

You're message indicates that you don't.

Consider for a moment, how would a CPU go about checking for a particular address being in cache in 2 clocks?

That's the beginning of your journey along the path to understanding the wayness of cache, and why it matters.

My earlier comment is absolutely correct: the cache in a $100 Athlon is effectively 325% larger than the cache in a $4,000 Itanium for a lot of code. Too bad Intel can't figure out how to make either victim or high set associative caches.

Ultimately, unless they can correct this, it may end up losing them a lot of their server business.


Perhaps I should clarify that I am comparing Itanium's main (L3) cache with Athlon's main (L2) cache. I think that's appropriate, too. Itanium's L1 and L2 combined (160K) are barely larger than Athlon's L1 cache (128K), so comparing Athlons's L2 with Itanium's L3 is reasonable. Itanium's 96K L2 is 6-way, while its 2 meg or 4 meg L3 is 4-way. Athlon's 256K L2 is 16-way.