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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Dan3 who wrote (53117)	8/29/2001 10:29:48 PM
From: wanna_bmw	Read Replies (1) \| Respond to of 275872

Dan, Re: Anand's benchmarks. You can expect those Xeon and Athlon MP scores to flip sides once Intel launches their server chips with hyperthreading enabled. Heck, a 40% IPC increase would even put Xeon ahead of Athlon MP in the Microstation benchmark. Wouldn't that be something? wanna_bmw

To: Dan3 who wrote (53117)	8/30/2001 12:39:39 AM
From: Saturn V	Read Replies (2) \| Respond to of 275872

Ref < The switched detail of which half of a harvard architecture P4 uses for its L1 is a minor detail - as you well know. > There you go go twisting facts again. Pete clearly stated twice that the Pentium 4 lacks a L1 data cache, and based a huge, lengthy, and incoherent analysis on that premise. A check of Page 1 of the Pentium 4 manual shows that it has both a L1 Data Cache and a L1 Instruction cache ( Trace Cache). Since the Athlon has such a superior cache, Tier 1 Server vendors are falling over themselves to introduce Athlon servers. The Transaction Processing Benchmarks will have Athlon based systems in the top 20 spots. The last time Elmer posted a link, I did not see one Athlon based system. Hm..m, oh I forgot ! The Transaction Processing Benchmark is a phony Intel designed benchmark, and Elmer is a minion of the Evil Empire ! My sincere apologies ! By the way (SARCASM MODE OFF), the thread has decided that AMD has a terrible marketing group. You would make an excellent marketeer for AMD. You communicate clearly and well, and can spin things to AMD's benefit in all possible situations. I really mean that as a compliment. However I shall not respond to your posts in the future, since they are hilariously ridiculous, and have no basis in reality.