To: Windsock who wrote (142441 ) 8/30/2001 4:54:07 PM From: pgerassi Read Replies (1) | Respond to of 186894 Dear Windsock: But you equate frequency with performance in the CPU world. You don't in the automotive world. All that needs doing here is to come up with an open standard (to guard against shenanigans by anyone) to measure CPU performance regardless of machine type, architecture or design. Then the clock rate of the CPU doesn't matter because everyone will ask for its "HP" performance number. You must be worried about such an eventuality, so you deliberately do not see it. Currently people have assumed that all x86 CPUs have the same torque or it was close enough to forget excepting rare cases like the Celeron 300 (not -A). Once the IPC ratio becomes >= 2, it becomes very obvious. At between 1.5 to 2, it is not as obvious but, if pointed out, it will be easily seen. At between 1.25 to 1.5, a much less obvious but, it takes more to make it visible. At less than 1.25, much work needs to be done to make someone see it. AMD is at the third range right now with Tbird and starts to go into the second with Palomino. Hammer with four major IPC boosts, integrated memory controller(s), doubling of both GP integer and SSE(2) registers, doubling of SSE(2) pipelines and 64 bit addressing and data, could easily reach more than 2x over P4 in single core situations and that means first range visibility. AMD probably does not have the resources for a low third range campaign but, can do a low second or high third range one. Palomino with Nforce will probably get to low second range and that is what AMD appears to be waiting for (or a return of the movers and shakers the 2nd week of September for greater impact (in the week after Labor Day, many may still be out)). Pete