Jozef, Re: "I guess you mean per cycle. Suppose Hammer improves IPC vs. Palomino, which has higher IPC than Thunderbird, which has higher IPC than P4, this could result that the performance levels of equally clocked Hammer chips would no longer be in the same ballpark as P4. It is within the realm of possibilities for IPC of Hammer to be 2x IPC of P4."
Well, let's think about that. First, what is Hammer competing against? Initially, it's not Pentium 4, but rather the .13u Xeon, which will feature the Northwood core, plus Hyperthreading.
Right now, I'll make a general statement, just for the sake of argument, that the Thunderbird gets 30% performance improvement over the Willamette. Palomino increases this gain by another 5-10%, for a total of 36-43% more performance per clock. This corresponds with the Palomino matching or exceeding the current Xeon processor, which currently has a 42% frequency advantage.
Let's say that Hammer arrives, and increases the IPC of over Palomino by another 10%. This is due to a larger L2 cache, presumably, as well as a few micro-architectural improvements. I will also assume that 64-bit readiness is still a year away, so the Hammer will compete on 32-bit software. This would give the Hammer a 57% performance advantage over a similarly clocked Willamette.
Let's also say that directly connected Hypertransport offers better bandwidth and lower latency for a 10-15% performance improvement, such that the Hammer can have up to an 80% performance advantage over the current Willamette.
Finally, let's say that a few 64-bit apps arrive, and the extra registers and 64-bit processing give the Hammer another 10% gain in performance. Overall, this would allow a Hammer chip to have a 2x IPC advantage over the current Willamette, which is what your prediction is. I am just proving that I can think along your same lines, not that I necessarily agree that all these performance increases will be possible.
But as we said earlier, Hammer is not competing with Willamette, but rather the .13u Xeon. In order to predict the performance of that processor, let's consider the performance increase that Northwood will have over Willamette. I am guessing that it will be in the 5-10% range, but since I gave Palomino the benefit of the doubt, I will give the same to Northwood.
Next, let's say that Hyperthreading gives a 30% improvement to IPC. Since Hyperthreading takes more advantage of server apps than anything else, it may end up being even better than this, but I want to be conservative. This will give a .13u Xeon processor a 43% performance advantage over Willamette.
At this point, the Hammer chip from before would still have more than a 25% IPC advantage over the .13u Xeon running 32-bit code, but due to the IDF demonstration on Tuesday, I'm willing to believe that Intel will continue to have significantly higher clock frequencies. I also believe Intel may have a few wild cards.
One of these wild cards could be a 533MHz front side bus. which I believe can offer a 5-10% performance advantage. I think another wild card would be the slow transition to newer software, which has been known to give the Pentium 4 a significant increase in performance, and the Athlon a smaller increase in performance. I think that optimized software for the .13u Xeon should give it a 40% improvement over time (compared to 30% for Hammer, simply on the basis that better coding produces faster code, and because Hammer also has SSE-2 instructions). Also, I consider platform changes to also improve performance. Right now, the current Xeon is on dual channel RDRAM with the i860 chipset. Next year, .13u Xeon processors will be on dual channel DDR200 chipsets from Serverworks and Intel. These will offer the same bandwidth, but probably much better latency, so I am guessing this will offer another 10% of performance improvement.
If we take the 40% performance improvement from software optimizations, the 10% improvement from transitioning to a 533MHz front side bus, and the 10% from using a dual channel DDR chipset, then the .13u Xeon will have a 140% advantage over the current Willamette by running tomorrow's optimized code. Similarly, Hammer will have a 160% advantage over the current Willamette by running tomorrow's 64-bit code, and a 135% advantage by running tomorrow's 32-bit code.
Taking my numbers seriously requires an imagination, since all of them are pulled from thin air. However, I have shown one possibility where the .13u Xeon can have a clock for clock advantage over the Hammer chip in 32-bit optimized apps, and only an 8% disadvantage against Hammer in 64-bit apps. But then again, you can argue any of my numbers to adjust the scores any way you want, but I think the point is that they are going to start converging in performance, but Xeon will still have the frequency lead. I don't think that even SOI will give Hammer the ability to match frequencies with Netburst, so there's a good possibility that Intel will still have the performance lead, even after Hammer launches.
wanna_bmw |
