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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: jcholewa who wrote (53374)	8/31/2001 12:01:34 PM
From: pgerassi	Respond to of 275872

Dear JC: Simple response, Athlon can decode 3 x86 integer instructions requiring address calculations all at once, execute them (as long as they are not dependent on each other) and retire them all in order due to there being 3 integer ALUs each having an address calculation unit. Thus in this not atypical case, Athlon has a 3 IPC rate for at least 1 cycle. They can also do 1 FP load/store, MMX, 3DNow (or SSE for Palomino) op, 1 FP add, and 1 FP multiply per cycle as well. Granted dependencies, cache subsystem and other restrictions reduce this to somewhere between 1 to 2 IPC or averaging 1.5 IPC. P4 averages 1.0 IPC over most code. Of course there are exceptions to both. Pete