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To: fyodor_ who wrote (53523)	8/31/2001 9:51:05 PM
From: wanna_bmw	Read Replies (1) \| Respond to of 275872

Fyo, Re: "Obviously the thruput will not be 2X of a single theaded system. But an improved thruput of 15%-40% sounds plausible. If memory bandwidth is the bottleneck, adding multiple processors (or multiple virtual processors) won't do a bit of good." It's not the resources, and it's not the memory. It's more like the management of both. The x86 instruction set does not favor Instruction Level Parallelism (ILP) nearly as much as many RISC architectures. Studies have found that optimized code rarely exceeds about 3 instructions per clock cycle. Optimized RISC instruction sets can't get much higher than 5. What multithreading does is increase the amount of Thread Level Parallelism (TLP), which helps the execution resources to be more fully used. The Alpha had the right idea building TLP into their EV8 core. Intel simply beat them to it. I don't know if Hyperthreading is as robust as the Alpha SMT, but the EV8 called for greater than 100% performance increase. It also had 4- or 8-way multithreading (can't remember which) compared the Hyperthreading, which is 2-way. I think the capability is there to do great things with it, but I also think it's a slow road towards really getting the best efficiency for the technology. But as you say, Fyo, it is very impressive that Intel was able to get 30% more floating point performance out of Hyperthreading, especially since the perception is that applications like Maya were already fairly efficient on working with processors. The applications for Hyperthreading in other apps seems astounding. wanna_bmw

To: fyodor_ who wrote (53523)	9/1/2001 1:56:38 AM
From: Saturn V	Respond to of 275872

Ref < If memory bandwidth is the bottleneck, adding multiple processors (or multiple virtual processors) won't do a bit of good. > The memory bandwidth is not the bottleneck. The bottleneck is the memory system latency. Each time there is a L2 cache miss, the processor stalls for more than a 100 cycles.[This is consists of sync delay with chipset,chipset delay time, and memory chip latency etc]. However if the extra virtual processor has the memory operand on chip,it will continue to execute full blast with all the processor resources. The double pumped ALU did not make sense with a single virtual processor. With two virtual processors, the double pumped ALU will be kept busy, and makes sense. The double precision intensive 3D renderer can also benefit if coded cleverly.The 3D double precision calculation part can be one thread, while the graphics display update can be another thread, and this thread will be integer intensive. The two threads can run in parallel, one using up the FPU and one using the ALU.