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To: fyodor_ who wrote (53572)	9/1/2001 2:32:52 PM
From: combjelly	Respond to of 275872

" It seems to me that unless you use heavy SIMD optimization, the P4 would often be decode-limited. Wouldn't adding a second decoder make HyperThreading much more interesting?" Probably. And that very well may be a future optimization. Intel is trying to push SSE and SSE2 because of the weakness you noted. dual decode units, a larger trace cache and better branch prediction are some obvious ways to improve the IPC of the P4, especially one that also has hyper-threading. The down side is all of these things also have some serious die size and/or clock rate limit implications.