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To: combjelly who wrote (53601)	9/2/2001 1:53:31 AM
From: wanna_bmw	Respond to of 275872

Combjelly, Re: "It was my understanding that the P4 ran at an effective clock rate of 50% when it had to hit the instruction decoder. The source was an Intel whitepaper on the P4 which gave that strong impression." Here's another paper from Intel. I think it clearly states what you are looking for (page 34). developer.intel.com "The front end of the Intel NetBurst micro-architecture has a single decoder that can decode instructions at the maximum rate of one instruction per clock." wanna_bmw

To: combjelly who wrote (53601)	9/2/2001 3:24:01 AM
From: Tenchusatsu	Respond to of 275872

Combjelly, <It was my understanding that the P4 ran at an effective clock rate of 50% when it had to hit the instruction decoder.> The P4 is pipelined just like any other modern processor. It does not slow down just to decode instructions. While the front end decodes instructions, the back-end executes instructions already decoded. Even if the decoder runs at half-speed (which it doesn't, AFAIK), the execution part of the pipeline still runs at full speed (even 2x the speed at certain points). Tenchusatsu