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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Dan3 who wrote (142620)	9/2/2001 1:43:33 AM
From: wanna_bmw	Respond to of 186894

Dan, Re: "Find the document where Intel details the parts of P4 that run at half speed - I'm no longer absolutely convinced it's the decoder, but, if not, then what is?" I've looked, and Intel doesn't seem to detail anything that runs at half speed. What I can point out, though, is that according to the micro-architecture spec here (on page 34 and 35): developer.intel.com It says the following. "The front end of the Intel NetBurst micro-architecture has a single decoder that can decode instructions at the maximum rate of one instruction per clock." This is as I know it, but Intel also claims this. "In the Pentium 4 processor implementation, the TC can hold up to 12K µops and can deliver up to three µops per cycle." As I've said, I believe the true trace cache issue rate is a full trace (6 uops) per every other clock cycle. But in actuality, what's the difference? By the time these uops get to the execution engine, they are being executed every clock. Similarly for the decoder, whether it does as the specs say, and decodes one instruction per clock, or whether it decodes 2 every other clock, or 3 every three clocks, the end result is that the instructions get decoded, and the trace cache eventually fills up with uops, and there is no bottleneck. I'm sure that some parts of the CPU run under different multiples of the clock (including half speed), but it's probably not important enough to be documented, as it probably affects the latching of proprietary buffering or some such undocumentable area. wanna_bmw