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To: fingolfen who wrote (142960)	9/9/2001 11:04:16 PM
From: THE WATSONYOUTH	Read Replies (3) \| Respond to of 186894

First, I have not seen the die map for the Power4. what percentage of the die is L2 cache? Is that L2 cache tightly grouped like a coppermine, xeon, or tualatin, or is it subdivided into blocks? If the "majority" of the die space is L2 cache (50% or thereabouts), then yes, some yield can be regained by cache redundancy and fusing bad areas of the cache. It makes sense that they would put that scheme in place. So far so good. You then go on to state the the area for the two cores is probably <200mm2. Where do you obtain that number? Is that total die size, or just core size (i.e. is the total die size 200mm2 or >400mm2, since you've already contended that the L2 cache makes up the "majority" of the die)? You do realize that to have a functional die BOTH cores must work? If only one core works, the die is "bad" (unless, of course, IBM has included extra fusable cores on the die... which doesn't strike me as helping a lot in the long haul). The fact that two cores need to work to have a functional die will reduce yield. If the cores are 200mm2 PLUS L2 cache... then the die size is certainly going to approach Itanium. Not sure how big McKinley is, although Intel indicates it runs 200+MM transistors. You go on to assert that Power4 is on a .18u process and is therefore not more aggressive... That is a non sequitur. Aggressiveness is a function of the microprocessor design, not purely the process. Any manufacturing process will have critical design rules (gate pitch must be greater than X, contact width can't be less than Y, etc.). An "aggressive" design will try to gain performance and/or die-size by pushing those critical design rules to the absolute limit with great frequency, whereas a less aggressive design will only use critical design rules for the most vital speed paths and functional units. Any “aggressive” design is going to suffer yield fallout because natural process variation will push too many features beyond the design rules into areas in which the process is not stable. I would therefore submit that your assertion that the Power4 is not aggressive was based on an erroneous assumption, and without looking at the Power4 design and understanding the critical design rules for the IBM process… I honestly don’t think that they’re going to tell us either so we can make a solid fact-based analysis! Based on these assumptions you declare your opponent wrong… I’m not sure you have a strong case, and yelling isn’t going to strengthen it… You then go onto a yield and cost/die model. First, you are assuming 80 die per wafer as you indicate a 10% yield will result in 8 die per wafer. This means you must be using the a number close to 400mm2 as the overall die size. How are you modeling the packing as with a die that large many die will be partials? Without die size and shape, it’s impossible to get a solid die/wafer calculation… unless, of course, you know what steppers IBM is using and know their field size as this would clearly be a 1 die/field processor. Given a 400mm2 die size or greater, I honestly don’t think IBM will get a theoretical yield of 80 die/wafer. You then assume an IBM wafer costs $2K to produce. Where did you get this number? IBM has always been the hallmark of advanced technology… at any price. IBM is not a volume fabrication unit, they never have been. They are an “art” fab. They do it better and faster, but not always cheaper. I’m not saying that IBM’s 0.18 micron wafer cost isn’t $2K, but I’d like to see some sort of reference here. If they’re using SOI I honestly doubt they have a $2K wafer cost. You then go on to indicate a module cost based on die cost plus packaging (again, where did you get the overall cost of packaging and assembly?), and once again declare your opponent “wrong.” Again, there seems to be a LOT of assumption in here, so that’s a very strong statement… Well I checked the M.P article again and some of my memory was off. I mistakenly thought it was 2M of L2 cache. It is 1.5M. So my 50% L2 cache area estimation is really about 35%. However, that doesn't change the argument at all. My assumption is an approx. 340mm2 chip. M.P. hinted around 400mm2 but I think he overestimated about 15%. I do indeed think the two cores (excluding L2 and the L3 directory) is less that 200mm2 (maybe 185mm2) And that is about the size of P4 on .18um without L2. So why do you think it should yield so low even with two cores? Is it smaller than Itanium or McKinley without L2 on .18? I would think it is. Your claim that somehow this process tests the .18um ground rules harder than the equivalent .18um bulk process is ridiculous. I've seen multiple checking decks run against critical groundrules on numerous designs. The number of minimum ground rule occurances will be in the hundred of thousands if not millions. Why do you think these designs are smaller and run faster from generation to generation? Designers will generally use anything that is given to them. And I have seen and understand the actual design rules since I worked in the area prior to retirement. Also, why do you think they call them rules? In fact, very often, designers will ask for specific ground rule waivers for critical designs. And pleeeese, don't tell me it is different at Intel. 80 die/wafer is a reasonable assumption for a 340mm2 die. Again, it has NO effect on the ultimate point of the argument. It is common knowledge thu the industry that it costs approx $1500 to $2000 to process a wafer thu any roughly equivalent high performance 6-7 layer metal advanced CMOS process (not counting depreciation). If you think it is closer to $200 or $20,000, then it makes no sense for me to discuss this with you. So, $2k is a conservative estimate accounting for the xtra cost of an SOI substrate. IBM competes on a foundry basis and so must have competitive pricing for equivalent processes. They can get some premium for something proprietary like Si/Ge BiCMOS or SOI but it is not the norm. The $2500 total module cost estimate was from M.P. And the dude who wrote that article is very well versed in this stuff. I believe it is lower based on any reasonable estimate of yield and have given you the assumptions I've used to arrive at that conclusion. If you think it is higher, please provide your assumptions which lead to that conclusion. I'd like to hear them. THE WATSONYOUTH P.S. I finally tracked down the URL. Much of what I've claimed cab be substantiated or argued based on this article. I find it just remarkable that no one on this thread has even read it. The URL has been posted at least three times when questions/issues arose in various discussions among many posters. For the last time.....will the process and design wannabeees please read this article so we don't have to go thru all of this preliminary stuff again. chips.ibm.com