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Politics : Formerly About Applied Materials -- Ignore unavailable to you. Want to Upgrade?

To: Gottfried who wrote (53471)	9/30/2001 11:00:15 PM
From: Jerome	Read Replies (1) \| Respond to of 70976

"Same as a market bottom.".What? No deep sounding fog horns? We are all victims of misinterpretation of trivial data. It seems like every talking head has got an agenda, while I suck up the losses. Like Nixon said, "You aren't going to have me to kick around any more"...(I'm running out of cash) Jerome.... Nixon's Checkers speech

To: Gottfried who wrote (53471)	10/1/2001 7:40:24 AM
From: Proud_Infidel	Respond to of 70976

Chartered 0.13micron Cu Process, 2.7-k Dielectrics Chartered Semiconductor Manufacturing, Ltd of Singapore has succeeded in developing a 0.13micron copper process with low dielectric constant (k) material of 2.7 to 2.8, and has demonstrated a six-transistor SRAM cell just 1.97square micro meters in size. The complete 0.13micron process has been jointly developed with Agere Systems (formerly the microelectronics division of Lucent Technologies) and is scheduled for manufacturing at Chartered as early as the first quarter of 2002. The copper and low-k material process has been jointly developed with Novellus Systems Inc. The copper process features higher speed circuit performance. "If a circuit is limited by interconnect, roughly 20 to 25% of speed is improved. We made sure of [this] with our simulation," said John Martin, chief technology officer at Chartered. The copper damascene process, partly provided by Novellus, includes barrier deposition, seed deposition and plating, but other copper process tools - including CMP and others - have come from other equipment companies. Chartered can select the best combination of individual tools from various suppliers, different from the approach taken by Applied Materials Inc, which provides a total solution of copper process, according to Martin. In the 0.13micron process, "We use both KrF and ArF excimer laser lithography, and will use it even in the 0.10micron process. Deep UV lithography will be continued to be used even for below 0.10micron process," said Martin. Below 0.1micron process, another challenge will emerge - that of the high-k dielectric material for the MOS gate insulator. Martin expects the 0.08-0.07micron process will use a different dielectric material, which will be developed through joint agreement with Agere Systems. (October 2001 Issue, Nikkei Electronics Asia)