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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: peter_luc who wrote (56989)	10/3/2001 5:43:23 AM
From: pgerassi	Read Replies (1) \| Respond to of 275872

Dear Peter_luc: It looks interesting. A minor jab that the upper level 1 cache is an instruction cache not as the labeled data cache. Many things are done to reduce the amount of instructions needed to be processed like hidden surface removal does for 3D acceleration and fill rate requirements. Some things like the do both ways increase the number of instructions to do. The latter could be a concern because most CPUs now are heat limited (current CPUs run faster if the rate of heat removal can be increased). Too many unnecessary operations could increase heat output with little increase, no increase or even some decrease of performance. If this core is either sampling or near sampling, Intel's Northwood may not be relevant anymore. Itanium and McKinley could go the way of the i860 or other mainstream VLIW CPUs, simply being ignored or dropped quietly. Matter of fact some software timing loops may be completely eliminated by this core as the operations are compressed away (a better timing loop could be made that refuses to be eliminated unlike traditional do nothing loops). It will be interesting how much faster per clock this Clawhammer could be than a Palomino. Pete

To: peter_luc who wrote (56989)	10/3/2001 12:36:18 PM
From: porn_start878	Respond to of 275872

A few observations/WAG in the light of this very intriguing article: Hans talks about two k8 project (k8-1 and k8-2). In fact I feel that k8-2 is k8-1's adaptation to P4. k8 initial objectives seemed to be Brute Force (IPC) : the dual execution core in a single CPU. When AMD learned about P4 20 stages pipeline and SSE-2 they scratched the Technical Floating Point project (or adapted it to) for SSE-2. They also took the decision to lenghten the pipeline in order to outperform the K7 clockspeed potential. There seems to be a lot of new stuff outside of the execution units : the prediction hardware looks far more advanced as well as the level 1 and 0 cache memory system. Also, as Hans noted, k8-2 would be a perfect chip for SMT. k8-2 is why hammer has been delayed, but it still could be a very good chip and there has been too much rumors/roadmaps on the chipsets to think that it'll come in 2003. I think begining Q4 (precisely in one year) will see a stealth launch (better than k7 due to the fact that it wont be AMD's first try as an infrastructure designer). My concerns are : -the P4 was originally designed with a long pipeline in mind, while k8 wasn't. -Jim Keller was one of the head of the k8 group, he left AMD... why? at least he left near the end of the development process so maybe he really wanted to be more than an employee and went to SiByte were he could have more weight. Let's see what we can learn from AMD's real k8 infrastructure presentation in two weeks. Maybe Hans missed a couple of k8-related patents : AMD is issuing 800 patents a year, I seriously doubt that only 13 are k8-related. WAG-Max