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To: milo_morai who wrote (57042)	10/3/2001 2:26:39 PM
From: Joe NYC	Respond to of 275872

Milo, First of all, we don't know if what Hans described is going to be the implementation of Hammer, that is, that if will have a single entry point of the pipe, with one decoder, L0/L1 instruction cache which would proceed to 2 insturcion execution cores. This would mean that Clawhammer would have 2 of these cores as well. It is only a speculation at this point. It may well be that the 2 cores of Sledgehammer will be more independent, with their own decoding, instruction caches, sharing only L2. In that case, Clawhammer would be a traditional design. The difference between the 2 schemes IMO would be that Hans's is targeted at fastest possible execution of single thread vs. ability to process more threads slower. I think in most single user environment, you want Hans's approach, which is to strive for the lowest latency in processing of an instruction thread, rather than concentrating on maximum throughput of severl threads executing at the same time. So anyway, it is not clear if Clawhammer will be single core or dual partial core. Clawhammer is 2-way, Sledgehammer starts at 4 ways, unless your thinking a Dual core cpu. No they don't. The both start with a single CPU package (whether it is single core or dual) and 99%+ of these CPUs will end there. It would be nice to have 4 way capability, but not at the price of sacrificing (or taking undue resources) from single and dual CPU implementation. The approach should be that these CPUs should be great CPUs standalone, with possibility of connecting more of them with HT. Joe