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Politics : Formerly About Applied Materials -- Ignore unavailable to you. Want to Upgrade?

To: robert b furman who wrote (53831)	10/4/2001 9:26:22 PM
From: Proud_Infidel	Read Replies (1) \| Respond to of 70976

Fujitsu to introduce 0.11-micron foundry process in early 2002 Semiconductor Business News (10/04/01 18:00 p.m. EST) SAN JOSE -- In early 2002, Fujitsu Ltd. plans to introduce into production a new 0.11-micron CMOS process technology with five-to-eight layers of copper interconnects and low-k dielectric insulators for silicon foundry services. The new copper CMOS technology will be aimed at expanding Fujitsu's foundry services for networking and communications ICs, according to the company's U.S. semiconductor subsidiary here. The new foundry process technology will be formally announced during next week's Fabless Semiconductor Association Suppliers' Expo in the Santa Clara Convention Center. "We also have plans to develop next-generation processes for all our key applications," said Keith Horn, vice president of marketing for the Systems Solutions Group at Fujitsu Microelectronics America. The Japanese chip maker said it is amassing a portfolio of application specific processes, including 0.35-micron liquid crystal on silicon (LCOS) for microdisplays, 0.35-micron CMOS image sensor technology, and high-voltage processes with 0.65- and 0.5-micron feature sizes. Fujitsu is planning to make available a new 0.35-micron process in the first quarter of 2002. For the new 0.11-micron foundry process, engineering teams at Fujitsu's Akiruno Technology Center in Japan have begun to accept GDS data for IC designs from fabless companies. The 0.11-micron process will have 0.07-micron L-effective gate lengths. Fujitsu claims the new process will provide the lowest power dissipation yet for foundry-fabricated wafers. Fujitsu said its process uses shallow-trench isolation, chemical-mechanical polishing (CMP), and cobalt silicide (CoSi2) in transistor gate and source/drain structures. Between five to eight levels of copper metal interconnect will be available for chip designs with a dielectric insulator that has a k constant of 2.6, said the company. ICs fabricated with the 0.11-micron process will have a 1.2-V supply voltage in the core. Analog and I/O blocks will be available with 2.5- and 3.3-V supplies. According to Fujitsu, the new process will enable foundry customers to pack twice the number of gates in a given area of silicon as existing 0.18-micron process technologies.