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To: reynoso who wrote (57491)10/6/2001 7:23:49 PM
From: ptannerRespond to of 275872
 
Reynoso, Re: Hammer & Itanium registers

Some info on Hammer can be found here: x86-64.org

in 64-bit mode the Hammers have an additional eight GPR (General Purpose Registers) plus all GPR registers are 64-bit instead of 32-bit and also adds an additional eight 128-bit SSE registers. See pages 8 and 9 of .pdf above.

Summary: 32-bit mode / 64-bit mode
GPR: 8x32-bit / 16x64-bit
MME/FP: 8x64-bit / 8x64-bit
SSE: 8x128-bit / 16x128-bit

I haven't perused Itanium information so hope someone else can provide register information.

-PT



To: reynoso who wrote (57491)10/6/2001 9:07:03 PM
From: TenchusatsuRead Replies (2) | Respond to of 275872
 
Reynoso, <how many registers does the Itanium have?>

128 general purpose (64-bit), 128 floating-point (64-bit), 64 predicates (one-bit).

(Hmmm, I wonder if I missed any.)

Tenchusatsu


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