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To: Elmer who wrote (145642)	10/18/2001 5:53:33 PM
From: wanna_bmw	Read Replies (1) \| Respond to of 186894

Elmer, here's the info from an Itanium and McKinley comparison slide. Itanium / McKinley Core Frequency: 800MHz / 1GHz Pipeline Stages: 10 / 8 System Bus: 64 bit wide / 128 bit wide Bus Speed: 266MHz / 400MHz Bus Bandwidth: 2.1GB/s / 6.4GB/s Integer Execution Units: 4 / 6 Loads/Stores: 2 loads OR stores per clock / 2 loads AND 2 stores per clock Issue Ports: 9 / 11 L1 Cache: 2x16KB 2 Cycle Latency / 2x16KB 1 Cycle Latency L2 Cache: 96KB 12 Cycle Latency / 256KB 5 Cycle Latency L3 Cache: 4MB 20 clk - 11.7GB/s Bandwidth / 3MB 12 clk - 32GB/s Bandwidth L3 Cache Location: Off-Die / On-Die Addressing: 44-bit Physical and 50-bit Virtual / 50-bit Physical and 64-bit Virtual Maximum Page Size: 256MB / 4GB They reiterated 1.7x SpecInt performance, but this time, they gave it in comparison with an Itanium at 379 SpecInt. Therefore, 1.7x equals ~644. Edit: I also seem to recall an off-the-cuff remark from another presentation that McKinley will fix a number of micro-architectural performance issues found in the current generation Itanium (and apparently there are quite a few known issues). Wen-Mei Hwu from IMPACT Research Group gave an insightful presentation on some of them. His future prognosis was that Itanium has a lot of performance headroom for the future that can be found through micro-architectural and compiler improvements. The first generation Merced should not nearly be considered a true indication of how IA-64 should perform. wanna_bmw