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To: combjelly who wrote (59368)10/19/2001 5:49:39 PM
From: wanna_bmwRead Replies (3) | Respond to of 275872
 
Combjelly, Re: "But so far, history has shown that it is harder to optimize the compilers than it is to throw transistors at the problem."

I have to disagree here. History has shown us that semiconductor manufacturers have thrown transistors at the problem, and up until now, things have worked out, but we are obviously hitting new walls, in terms of power dissipation (discussed at IPF), limits of ILP (also discussed during MPF), and system design challenges (again, discussed at IPF). Going the way of frequency directly affects power, EMI levels, system design levels, and others, while going the way of IPC increases die size, adds to thermal problems, and affects things in different ways.

Up until now, there hasn't been a lot of desire to use the compiler to increase CPU performance, but given that the old ways of increasing performance have become increasingly difficult, addressing the compiler is likely to be revisited. EPIC is not an inherently in-order design, although the first iteration is designed to operate this way. Future designs may incorporate some out-of-order principles, so that the best of both worlds can be achieved.

Additionally, changes within a compiler can be tested and implemented in real time. Software only needs to be recompiled to take affect. Hardware changes, on the other hand, require a long design and verification process that can easily last years. I think that this architecture shows a lot of promise, even though many people expected more the first time around. Fortunately, I see even the near future holding a lot of headroom for Itanium.

wanna_bmw



To: combjelly who wrote (59368)10/19/2001 6:08:50 PM
From: wanna_bmwRead Replies (4) | Respond to of 275872
 
Combjelly, Re: "So will Itanium be the future? I am dubious, if only because any architecture that has been worked on for close to a decade before it manages to ship, and then with only limited performance, has a serious uphill battle on it's hands."

First, Itanium itself has not been around for close to a decade. Wen-Mei had an Itanium timeline in his presentation that showed Intel and HP as announcing the Itanium project in late 1997 - 4 years ago. That is pretty typical for a processor architecture. However, work related to advances in ILP compiler technology can be traced all the way back to 1987. In 1995, Intel and HP first began their alliance, but work on the architecture infrastructure began long before the processor did.

Given that Itanium is not as old as you think, you may want to revise your gloomy outlook towards the architecture.

"By the time that the 2nd or 3rd generation is out, the other chips out there will have advanced also. Ok, it won't have to worry about EV8 now, but the next gen. Power4 or AMD Dog series should be out there."

I don't think Intel has much to worry about IBM's Power4. That architecture comes with a price. At 1.1GHz, IBM confessed that the die dissipates 150W of power (and that's with SOI!). Not only that, but with prices starting at $450k (according to their web page), power4 isn't likely to compete in the same <$100k market that Itanium is originally aiming for.

As for AMD's processor lines, Intel will have their 2nd generation McKinley processor 2-3 quarters before the Hammer even launches (assuming a Q402 or Q103 launch for Hammer and a Q202 launch for McKinley). The 2.5 generation Madison will be out in the first half of 2003, meaning that AMD's 2GHz Hammer will compete with Intel's 1.5GHz+ Madison (my WAG on Madison clock frequency) that may just outperform it. AMD's K9 won't ship for at least 3-4 years after K8 launches, so I estimate 2006 at the earliest. If things continue to progress well, Intel will have their 3rd generation Itanium well before that. Itanium has a good future, and competition isn't going to bury it any time soon.

"A Hammer with a revised core and SMT (assuming that is what is in the next gen. Hammer) would be a formidable competitor to future Itaniums..."

Fred Webber said that although Hammer architecture was designed to support SMT, there are no plans to implement it at this time. Considering how difficult SMT is to implement (it took Intel more than a year after Pentium 4 launch to enable it, when it should have been available from the beginning), I don't expect to see it from AMD until 2004. Madison will have ramped up quite a bit by then, and there may even be signs of Madison's successor. Since Intel has already stated that they are pursuing SMT and CMP for Itanium, it's possible that an Itanium CPU in the 2004 time frame will have these features implemented, which would make it quite competitive against a similarly formidable Hammer.

wanna_bmw



To: combjelly who wrote (59368)10/20/2001 9:32:47 AM
From: dale_laroyRead Replies (1) | Respond to of 275872
 
>So will Itanium be the future?<

The short answer is yes! With Alpha out of the way, the only architectures that stand any chance at all of competing in the target markets of Itanium are SPARC & Power, and neither SUN nor IBM is particularly eager to push these as a merchant chips.

The long answer is, how stable is this market segment? For years the target markets of Itanium have been eroded by Xeon. I say eroded because Xeon is not going into the types of systems at which Itanium is targeted, but rather the entire paradigm is changing with the emergence of new categories, such as thin servers, that are displacing the old.

Hammer/K9 will not compete with Itanium in the types of systems at which Itanium is targeted. But, Hammer could displace Xeon in the types of systems that will, in turn, displace the types of systems at which Itanium is targeted. The key here is whether Xeon is adequate to sustain the assault on the traditional markets all by itself, or whether x86-64 will be needed in future thin servers and other threats to these markets. If Xeon is sufficient, Hammer could fail almost completely. If Xeon is inadequate to address the changes of this market, x86-64 will eventually win.