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To: combjelly who wrote (59814)	10/23/2001 6:19:31 PM
From: wanna_bmw	Read Replies (2) \| Respond to of 275872

Combjelly, I think you are reading too much into the slides. They may just be using 1ns as a relative baseline, rather than an absolute measurement. Or it may not mean anything at all. These slides could have been made by the technical marketing department. The important thing is what Fred Webber said, not the fine print on his Powerpoint presentation. wanna_bmw

To: combjelly who wrote (59814)	10/23/2001 6:26:20 PM
From: TGPTNDR	Read Replies (1) \| Respond to of 275872

CJ, You got me curious. Where are the slides you're musing over? tgptndr

To: combjelly who wrote (59814)	10/24/2001 10:09:48 AM
From: pgerassi	Read Replies (1) \| Respond to of 275872

Dear Combjelly: Looking at the lines nest to the times you would notice that they start counting after the execute stage. Thus, 2 stages equal 1ns (L1 hit), 10 stages equal 5ns (L1 miss, L2 hit) and 22 stages equal 12ns (L2 miss, but not counting actual DRAM latency (for 1T CAS2 DDRDRAm is 9 cycles for a L2 cache line fill single channel (90s at PC1600, 67.5ns at PC2100 and 54ns at PC2700))). All stages are 0.5ns long or Hammer running at 2GHz (probable speed at 0.18u bulk). Pete