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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Joe NYC who wrote (59834)	10/23/2001 7:27:25 PM
From: wanna_bmw	Read Replies (2) \| Respond to of 275872

Joe, I agree that the slides are deceptive, and I thought so at the conference as well. Nonetheless, Webber mentioned nothing about different clock domains, or anything along the lines you are suggesting. I was sitting next to some other guys, and we figured it was a marketing mistake to label the units as 'ns', rather than absolute integer numbers. Webber's main focus was Hammer's ability to cut down memory latency, while at the same time providing very scalable and easy to configure components. Interestingly, the flexability of the Hypertransport protocol has been somewhat glossed over on this forum, but Webber found it to be Hammer's greatest strength. AMD is aiming for Hammer to realize lower cost, high performance systems, through the use of fewer components on a system board. Thus, having the memory controller integrated onto the CPU. Others at the conference addressed the issue of newer memory technologies making a Hammer CPU obsolete, but Webber maintained that CPUs progress faster than memory technologies, and as new memory technologies arrive in volume, there would be newer CPU revisions to support these technologies. It was certainly smart of them to support 16-byte wide PC2700, since that will provide a lot of bandwidth. Another thing that Webber stressed were the new RAS features available for Hammer, such as memory scrubbing and ECC chipkill. Although these are not new technologies to the industry, they are very important for high reliability systems, and Webber figured that AMD ought to have them, too. One thing that Webber tried to avoid was comparing Hammer to the K7. The slides were even made to look quite different from the K7 slides, although it's obvious to the keen observer that Hammer and K7 share many similarities. Frankly, I'm not surprised they share the same micro-architecture, since I think that most of the work is going into creating the cache coherent memory controller, which is a great step for AMD. Although AMD's transfer protocol is kind of primitive (in my opinion since transactions are simply forwarded from CPU to CPU, rather than carrying info about the cache state or the destination), I think they have the bandwidth to support this easier implementation. At the end of the conference, I felt confident for AMD, as this really seemed like a solid product for them. Later on, I had second thoughts, but that was only based on the fact that we haven't had any confirmation on a first tape out of Hammer. I don't know if it has taped out yet, but if it hasn't, AMD still has a lot of work ahead of them, and a 2003 launch is looking more like reality. Hammer is an aggressive design. Maybe not so much as K7 (with respect to K6), but it's still a major change to AMD's current paradigm. If there's anything else you want to know, feel free to ask. wanna_bmw