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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (60248)	10/25/2001 5:01:59 PM
From: jcholewa	Read Replies (2) \| Respond to of 275872

> It's unlikely that a 12-stage pipeline can even come close > to the clock speed of a 20-stage pipeline. Either that, > or Intel is severely underestimating the benefits of SOI. I should note that VIA will have a 16-stage processor in a couple years. I would submit that the K7 could easily outclock it on equivalent process technology, and a K6 might be able to at least approach it. Number of stages isn't the determinant of clock speed, though it's an excellent way of generating a rule of thumb. If there were some way of figuring it out, the better metric would be the delay for the most complex stage. If you had 19 stages that took 1ns, and one stage that took 1ms, then you would have a processor that could not run faster than 1KHz. Granted, I don't think that this is the case with the Pentium 4, but I just wanted to keep you aware that it's more complex than it seems. The K7 is going within between 20% and 30% of the P4 clock speed. Paul DeMone has an interesting argument for why P4 will ramp better on smaller process technologies compared to the Athlon. He states that the P4 includes in some areas wire delays as stages. This may be an advantage for Intel; however, if this is not the case, then there is not too much reason to assume that the K7 family will not be able to remain within 30% of the P4 successors. There is a school of thought that says that the processors are more heat limited than transistor limited, and that AMD's process may address that more elegantly whereas Intel's process pays more attention to transistor switching speeds. Anyway, it's difficult to say what kind of boost AMD will get from K7 to K8. It looks like their pipeline rebalancing act was done pretty much on the front end, with the decoders. How do you know that K7 wasn't being held back by the decoder taking too long to decode? If it was, then the increase in stages (unless I'm mistaken about these stages being more numerous; I tried to do a quick check, but I'm not good at reading these diagrams sometimes. :) There's one other thing: Part of that P4 general pipeline is running at twice the frequency as the rest of the processor. What effect would this have? If even only one stage of the processor has to run at twice the frequency of the other stages, that stage has to be far less complex than any other stage. If that stage isn't half the "length" of the most complex regular stage in the pipeline, then this stage would hold back the processor. For all we know, the Pentium 4 may not be ramping as high as a classical 20 stage processor normally wood. This was one of Scumbria's sore points about the P4, if I accurately recall it. Of course, this all means nothing until we get more hints from these companies. :)