Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: fingolfen who wrote (146441)	10/31/2001 1:56:43 PM
From: wanna_bmw	Read Replies (1) \| Respond to of 186894

Fingolfen, Re: "The notched poly was used beginning with coppermine on 0.18 micron which resulted in 100-110nm gates. As far as I know they're still using it even on the P4 (since it's the same process)." I don't remember where I heard this before, but I'm fairly certain that Intel did, in fact, stop using that technology. Notched gates had their benefits and their sacrifices, but apparently Intel thought they could push their .18u process without it. Maybe they were able to get 100nm gate lengths using a straight wall method. After all, if AMD is able to get theirs down to 70nm, I don't see why Intel wouldn't push their .18u process a little further as well. I don't know how much AMD's yields are impacted by their aggressive measurements, but I assume going that small isn't without its compromises. At any rate, back to your question, I think you should try searching for information on this forum. I think I remember more than a few people mentioning that Intel no longer uses notched gates. Perhaps a search of posts from semiconeng can answer your question. wanna_bmw