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To: NightOwl who wrote (79527)	11/2/2001 8:46:13 AM
From: Bilow	Respond to of 93625

Hi NightOwl; Yes, the AMD Hammer needs no "North Bridge", it's an integrated processor (like Timna was going to be). I'd guess that Hammer has embedded cache memory, but I'm only guessing. No, the Hammer will only have one memory controller, and that is the one that's embedded in the Hammer chip. I get the impression that the simplicity here is escaping you. All they did was take the North bridge, which interfaces to memory and to the CPU, and the CPU, which interfaces to the North bridge, and combine the two chips into a single chip. That eliminates the connection between the CPU and the North bridge as a source of expense and latency. Re: "If this embedded controller is serving main memory directly why the heck would the interface top out at only 16 bytes/128bits? Shouldn't it include 256bits for the latest, greatest, fastest DDR SDRAM? Or is the 128bit max dictated by the 64bit CPU and 64x2 bit DDR bus?" Current DDR chipsets are 64-bits wide. That means one memory channel. The Hammer is 128 bits wide, which is two DDR SDRAM memory channels. That means you'll have to install DIMMs in pairs, like with the i850 P4. If they went to a 256-bit wide DDR interface they'd have to install memory chips 4 at a time. While this would be feasible, I'd guess that the additional performance wasn't sufficient compared to the additional cost. Graphics cards don't require DIMMs, so there's no "4 at a time" issue with x256 widths. Re: "Or is the 128bit max dictated by the 64bit CPU and 64x2 bit DDR bus?" I don't know the details of Hammer, but I'm guessing you're generalizing from the Athlon, which does have a 64-bit wide x2 DDR FSB (Front Side Bus). With Hammer, the FSB is gone, it no longer exists. The instruction size has nothing to do with the FSB width. Instructions spin by at rates far higher than DRAM can provide, so it's natural to collect up multiple accesses into wider accesses. In fact, the logical width of the Hammer's accesses to DRAM will have to be 256 bits. That's because the shortest access to DDR SDRAM is 2 words, and each word will have 128 bits. Re: "Could they go to a 256bit interface with QDR-DDR to keep a match?" There is no match, but if there were, they'd be scaling in the wrong direction if they did that... QDR would want a narrower interface, not a wider one, than DDR. -- Carl