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Technology Stocks : Applied Materials No-Politics Thread (AMAT) -- Ignore unavailable to you. Want to Upgrade?

To: Proud_Infidel who wrote (309)	11/6/2001 12:29:24 PM
From: Proud_Infidel	Read Replies (1) \| Respond to of 25522

Toshiba, Fujitsu report 100-nanometer process gains By Paul Kallender EE Times (11/06/01 12:17 p.m. EST) TOKYO — Japan's efforts to develop 100-nanometer and finer process technologies have advanced on several fronts recently, with Toshiba Corp. and Tokyo Electron Ltd. working together to improve low-k dielectric annealing processes, and Fujitsu Ltd. separately reporting a deuterium-based annealing process that it believes will help overcome the hot-carrier problems that threaten to shorten the life of deep-submicron ICs. Toshiba and Tokyo Electron said they have developed a low-k cure process using electron beams that slashes thermal cure times and lowers the thermal budget compared to conventional furnace methods. The electron-beam method could help Toshiba overcome two major obstacles posed when low-k dielectrics are used to insulate copper lines in logic processes with 100-nm and finer linewidths. High-temperature curing to secure the films causes diffusion into the copper wires, the companies said. The Toshiba-Tokyo Electron process uses 19 electron beam tubes to cure JSR Corp.'s low-k dielectric materials on wafers at about 35°C in two minutes — much quicker than the 30 minutes required of a typical 400 ° furnace, said Nobuo Hayasaka, senior manager of Toshiba's advanced ULSI process engineering department. Moreover, the film's mechanical strength is about 1.9 times better than the conventional hot-plate system and achieves an equivalent dielectric constant and better uniformity, Hayasaka said. "Here we have a huge improvement in cure time and tens of percents of improvement in mechanical strength with the electrical properties unchanged," he said. The electron-beam process uses a cure chamber, a dry pump and a gas supply unit. After coating and pre-baking JSR's low-k material at 80°C then at 200°C, the wafers get slammed with electrons, which cure the material to a dielectric of 2.91 — just about right for 100-nm process requirements. Brainstorm benefits The approach arose out of brainstorming sessions between engineers from both companies, said Hiro Ishida, project leader for Tokyo Electron's ultra low-k project. The film's robustness results from a network of molecule chains formed through extensive cross-linking of each polymer, Ishida said. While the exact electrochemical characteristics and physics are still under investigation, the electron-beam process is an excellent means of stimulating a chain reaction in the polymer to form the strength-boosting cross linking, Ishida said. The process' throughput of about 60 wafers per hour per chamber could make it scalable to mass production, the companies said. The process has been used on 100 wafers with satisfactory results, and is considered a candidate for Toshiba's 100-nm logic process, said Hayasaka. Toshiba will decide whether to deploy the process on its 100-nm platform in the spring of 2002, he said. Carrier control Addressing another problem with deep-submicron process geometries, Fujitsu Laboratories said it has redevelop a deuterium annealing process that will help chips withstand the so-called hot-carrier problem. Device makers traditionally rely on a hydrogen gas anneal that degrades performance. Fujitsu became concerned after data suggested that hydrogen bonds will become too weak for devices made on 100-nm and narrower process nodes, said Osamu Ueda, manager of Fujitsu's nanoelectronic materials research and engineering laboratory. Fujitsu researchers have long understood that annealing in deuterium gas creates more robust bonds, but no Japanese company has successfully applied the technique to chips made in a deep-submicron process, Ueda said. Research by Fujitsu on its 0.13-micron process has demonstrated that the technique can nearly double the lifetime of a chip made in that process, said Hiroshi Yamada-Kaneta, senior researcher at the company's nanoelectric lab. With minor alterations, the technique could solve the hot-carrier problem for chips with 90-nm linewidths, he said. "In the late '90s, many Japanese companies tried this approach to improve LSI performance at, for example, the 0.35-micron level and they succeeded in developing LSIs with excellent lifetimes," Ueda said. "But below this process level, nobody could manage to succeed and nobody really understood why deuterium worked." Research implied that deuterium atom bonding is more robust because deuterium's mass is twice that of hydrogen atoms. "The physical explanation was too simple," Yamada-Kaneta said. "I found there was a much more complex and subtle and elaborate mechanism at work," he told EE Times. Yamada-Kaneta found that deuterium atoms have a lower vibrational energy than hydrogen, which affects vibration in the silicon substrate. This enables deuterium atoms to simultaneously take more hits and to absorb more energy before they are shaken out of their bonds. Further, he found deuterium has a two-stage energy "relaxation process" with a very high stretching mode and a rotation mode that is synchronized with the vibration within the silicon, meaning energy is more easily released into the lattice, he said. But the deuterium process costs much more than conventional annealing, and the technique has not yet been applied to a production process. Fujitsu hasn't yet decided whether to introduce the annealing technique into its 100-nm process, said Ueda. "We are convinced that conventional annealing techniques will completely fail in achieving sufficient anti-hot-carrier reliability for next or following generation fine-scale devices. Therefore, use of the deuterium technique will be inevitable for near-future fine devices," Yamada-Kaneta said.