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To: Jim McMannis who wrote (62817)	11/8/2001 12:54:15 AM
From: wanna_bmw	Respond to of 275872

Jim, Re: "I knew that the logistics of integration would hold back the clockspeed relative to the stand alone Celeron/P-III core." So I suppose the "logistics of integration" apply to Celeron and Pentium III, but not to Hammer, which also integrates a memory interface? wanna_bmw

To: Jim McMannis who wrote (62817)	11/8/2001 12:34:39 PM
From: Tenchusatsu	Respond to of 275872

Jim, <I knew that the logistics of integration would hold back the clockspeed relative to the stand alone Celeron/P-III core.> I know that Timna was divided into two clock domains. One domain was for the processor core, and the other was for the MCH and the graphics. The former ran at speeds you'd expect from a processor, and the latter ran at speeds you'd expect from a chipset. I don't know how the MCH and the graphics core would have any effect on the speed of processor core. I can't see how it would, though. Tenchusatsu