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To: Tenchusatsu who wrote (63087)	11/9/2001 1:50:10 AM
From: pgerassi	Read Replies (2) \| Respond to of 275872

Dear Tench: Sorry, registers (RISC ones in the execution portion) are part of resources in IA-32 systems, ala P4. There is a stage in the P4 pipeline to assign registers to uops. If there are more RISC registers, some uops that would be blocked are available to be processed. In any OOO machine, SMT only allows two independent streams to have a crack at getting resources. If fact, SMT requires there to be unused extra resources else it does not do anything to enhance performance. That there are two virtual sets of registers only exists as map onto the register rename pool. Since that is how these are truly implemented, SMT could in fact slow down a CPU for any given thread and in some cases even both threads would be slower than just one fast thread. This is probably a factor due to the length of the P4 pipeline. Thus, any P4 with SMT will require additional reorder registers in the pool to prevent this bottleneck from showing up. Note, this is different from CMP in that CMP doubles the whole execution engine (minimal case, typical case includes decoding, etc.) thus, doubling reorder registers and execution units. CMP completely makes independent the two execution engines for there are virtual maps for each reorder register pool. Thus, CMP will have a higher throughput than SMT. Sledgehammer will be the typical CMP with two sets of L1, decoding, register rename pools and execution engines. As to the model numbers, NW will not be as fast as Tbird clock for clock. Since it will be slower, NW in MHz will be slower than the XP model numbers. The only question is how much slower will NW be than an equivalently clocked Tbird? Pete