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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Petz who wrote (63213)	11/9/2001 12:49:30 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 275872

Petz, <Register renaming is much more effective if there's more registers available, includng registers that the programmer/compiler knows nothing about and hasn't explicitly coded.> If the compiler knows nothing about the additional registers, it has to create code that does a lot of swapping between register and data. More registers means less swapping, which leads to more compact code. However, the compiler needs to know about the extra registers before it can produce code that swaps less. Even AMD said this during the last Microprocessor Forum. They took their ubiquitous slogan, "Performance = IPC x Frequency," and added that number of instructions also matters. They argue that extra registers will lead to more compact code, i.e. fewer instructions to execute for a given task. They're right, of course, but they forgot to mention one thing: The only way to shrink code is to recompile it. Other than that, the additional registers provide no benefit. <Who's to say [if Hammer will or will not have SMT]> If anything, the earliest SMT can appear is during the K9 timeframe. After all, Athlon looks a lot like Alpha 21264 (EV6), and Hammer looks a lot like Alpha 21364 (EV7). Alpha EV8 was going to have SMT (before its demise), so if K9 is going to look like EV8, it will have SMT. Tenchusatsu