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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Bilow who wrote (79733)	11/12/2001 3:50:48 PM
From: Jdaasoc	Read Replies (1) \| Respond to of 93625

carl: spot market DRAM going wacky 128 MB PC133 $ 17 and climbing 256 MB PC133 $ 33.90

To: Bilow who wrote (79733)	11/13/2001 3:33:19 PM
From: Bilow	Read Replies (1) \| Respond to of 93625

Hi all; Rambus moron speaks out on Rambus technology on Fool thread, in answer to my post here: #reply-16644679 Re: "From this post, Bilow claims to be an expert in the memory field. However, from his above quoted response, it tells me he is no expert. His comment that each bit travels down the wire twice is just a bunch of BS nonsense. There are MANY reflections on the rambus bus. Bilow seem to think there is only one reflection at the controller interface. Not true. Any HF technician (not to mention an engineer) would know this. Then, worst mistake of all, the reflections have nothing to do with the question of how many bits are stored on the bus at one time. He seens to think the number of bits are doubled because they are reflected and hence still on the bus. This is plain gargage! All reflections are NOISE on the bus. As the rambus channel has very good noise immunity, these reflections are immaterial to any intelligent discussions." boards.fool.com For reference, here's my passage: "(2) Each bit travels down the wire twice (during a memory read). They are emitted from the memory, travel to the memory controller, are reflected, and travel back down the wire to the other end, where they are absorbed by the termination." #reply-16644679 It's pointless to explain how this works to mom and pop. But for those select electrical engineers who doubt that anyone would design a memory system with such a stupidly complex reading scheme, here's the Tektronix description of a Rambus memory read. Note that "RAC" is the driver, and is at the opposite end of the bus from the termination resistors: Probing for READ Data The RSL (Rambus Signaling Levels) logic used on all high-speed Rambus signals utilizes a low-voltage-swing over a carefully controlled low-impedance transmission line. The signal path design is carefully tuned for optimum signal quality and power dissipation through the use of single-ended terminations. One of the by-products of this bus topology is the unique behavior of the DATA signals during a data Read operation (when READ data is driven on the bus by an RDRAM). In normal operation, the data simply cannot be viewed with conventional acquisition techniques. Look at Figure 22 to understand why. The DATA and control (ROW & COLUMN) signals are parallel terminated (to Vterm) at only one end of the transmission line (opposite the memory controller/chipset ). The other end of the line is effectively only terminated by the series output impedance of the Rambus ASIC Cell (RAC) in the chipset, a form of termination that disappears when the bus is reversed for READ data. Therefore when an RDRAM delivers a DATA signal during the Read operation, the signal on the bus encounters a perfect termination at one end (to the right in Figure 22) and a very high impedance on the other (to the left in Figure 22). When the signal encounters the high impedance at the RAC, reflections occur. At the RAC connection point itself, the reflections are virtually in phase with the incident waves, and actually double the signal’s amplitude at that point. The RAC therefore receives full-amplitude DATA pulses. tektronix.com If you can't work out the fact that a given read bit travels the bus twice from the above, well God help you, you're not much of an electrical engineer. It's not possible for me to educate the moron universe, so I'll leave it there. But the reason for discussing this is PTNewell's denial that a Rambus channel had multiple bits on a wire at the same time. Here's the relevant passage from the Tektronix manual on PC800 RDRAM, which should make it clear that PTNewell was wrong even to moronic mom and pop investors who don't know what "termination" means: "Consider this startling fact: at a given instant in time, approximately three bits of information are in transit between a source and a destination (for example, between the memory controller IC and an RDRAM)." tektronix.com The subject being discussed was PC1066, and of course PC1066 has faster bits, and so more bits on the wire than PC800. And the fact is that in reading, there are as much as twice as many bits on a wire because the wave fronts carrying the information are only terminated at one end. The poster goes on to complain about my characterization of PTNewell's famous "Laws of Physics" post: "Evidently, our expert Bilow doesn't understand Maxwell's equations. Ptnewell never stated that DDR won't work. He just said that DDR has to contend with more noise and EMI because DDR uses a 2.5V step while RDRAM has a 0.4V step." Here's the post, you be the judge: "DDR-200 may or may not be practical in a PC. The DDR noise problem is not a fiction of Intel, it is fundamental physics. ... DDR-266 is quite improbable in a PC setting. Unfortunately for DDR, basic physics cannot be finessed." messages.yahoo.com Whatever. The fact is that Intel seemed to find a way to "finesse" the laws of Physics. And now, beyond "improbable" as it may seem, PC2700 is being sold and PC3200 is talked about. -- Carl

To: Bilow who wrote (79733)	12/8/2001 11:05:38 PM
From: Bilow	Respond to of 93625

Hi all; Samsung puts lie to PTNewell's claim that PC1066 would only have one bit on the bus. Here's the original post by PT, in his inimitable, pseudo-intellectual style: ... Now if I were prone to such pettiness, I would address something recent, and something posted on this board. Say, elixe's recent claim that PC1066 will have 4 bits simultaneously on a data bus. Since the typical length on a RDRAM board is about 25 cm, and the speed of light is 3x1010 cm/s, in fact a bit takes less than 25 cm/(3x1010 cm/s) = 0.8 nS. Thus PC1066 should usually not have more than ONE bit on the bus, and never the 4 that elixe claimed. Such a counter-thrust would be both more relevant and more topical (and of course, elixe has, I believe, not pointed out his own error). In short, if I were inclined to join in such petty attacks, I would at least take the care to make them to the point. ... boards.fool.com Here's Samsung's application note that explicitly states that long channel RDRAM has up to 5 bits on the channel at a time, while even "short channel" RDRAM has up to 3 bits. Note that tTR is the time for a single bit: samsungelectronics.com Gosh! Samsung sure has a lot of recently written application notes for DDR: samsungelectronics.com -- Carl